Automatic test equipment for integrated circuits

• US 4,763,066 A
• Filed: 09/23/1986
• Issued: 08/09/1988
• Est. Priority Date: 09/23/1986
• Status: Expired due to Term

• Current Assignee: Huntron Instruments Incorporated
• Original Assignee: Huntron Instruments Incorporated
• Inventors: Howard, Alan D., Yeung, Paul K. K., Hoo, James W., Pennock, James L.
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): BURNS, WILLIAM
• Application Number:
  US06/910,483
• Time in Patent Office: 686 Days
• Field of Search: 324/73 R, 324/73 AT, 324/73 PC, 324/158 R, 340/715, 340/722, 371/25, 364/487
• US Class Current: 324/73.1
• CPC Class Codes: G01R 31/31915 In-circuit Testers
• CPC Class Codes: G06F 11/277 with comparison between actual response and known fault-free response

Abstract

The apparatus (10) includes a semiconductor tester (12) which in operation produces an analog signature signal relative to a circuit node of an electronic circuit, such as a pin connection of an integrated circuit. The analog signature signal is the result of horizontal and vertical signals which are also directed to an integrator/A-D converter (44) which produces therefrom a set of four digital signals representing said analog signature. These digital signals are then compared in a computer (50) against reference digital values for the same circuit node of the same electronic circuit which is known to be good. If the digital signals are not within a selected range relative to the reference digital values, the analog signature of the circuit node is displayed for inspection and evaluation by an operator.

Claims

1. An apparatus for testing an electronic circuit, comprising:

means for connecting an electronic circuit having an operating condition which is to be tested to said apparatus, said electronic circuit havinq a plurality of selected node points;

means for automatically applying an electrical interrogation signal to said selected circuit node points in turn;

means for automatically obtaining from said circuit node points in response to said interrogation signal two electrical signal waveforms, one of which is a current waveform and the other of which is a voltage waveform, both of which have positive and negative portions, wherein said two waveforms, when combined, form an analog signature which is indicative of the operating condition of the electronic circuit relative to said circuit node points and wherein the apparatus includes means for combining said two waveforms to produce said analog signature;

means for integrating the positive and negative portions of one cycle of each of said two waveforms;

means for generating four digital values representative of the integrated portions, respectively, of said two waveforms;

means establishing and storing reference digital values for the selected circuit node points;

means comparing the generated digital values for each selected circuit node point with the corresponding reference digital values therefore and identifying those circuit node points having a generated digital value which is within a selected range relative to said corresponding reference digital value; and

means for producing and displaying the analog signature for those circuit node points which do not have a generated digital value within said selected range.

2. An apparatus of claim 1, wherein the circuit to be tested remains in-circuit and is in a power-off condition when tested, and wherein said interrogation signals are provided directly by the apparatus and not as a result of the circuit to be tested actually operating.

3. An apparatus of claim 1, wherein the electronic circuit to be tested includes integrated circuits and said connecting means includes means providing separate connections for each pin of each integrated circuit in turn in said electronic circuit.

4. An apparatus of claim 3, wherein said connecting means includes means for connecting said apparatus to a wide variety of integrated circuits.

5. An apparatus of claim 1, including means for entering and storing information concerning the electronic circuits to be tested.

6. An apparatus of claim 1, wherein the analog signature is obtained by applying one electrical signal waveform to a horizontal connection of a visual display device and the other electrical signal waveform to a vertical connection of the visual display device.

7. An apparatus of claim 1, wherein the reference digital values are obtained from an electronic circuit known to be good.

8. An apparatus of claim 1, wherein the displaying means includes means for displaying the analog signatures which are not within the selected range following the complete testing of at least one integrated circuit, the display of said signatures being in order from most different to least different relative to the selected range.

9. A method for testing an electronic circuit, comprising the steps of:

connecting an electronic circuit having an operating condition which is to be tested to said apparatus, said electronic circuit having a plurality of selected node points;

automatically applying an electrical interrogation signal to said selected circuit node points in turn;

automatically obtaining from said circuit node points in response to said interrogation signal two electrical signal waveforms, one of which is a current waveform and the other of which is a voltage waveform, both of which have positive and negative portions, wherein said two waveforms, when combined, form an analog signature which is indicative of the operating condition of the electronic circuit relative to said circuit node points;

integrating the positive and negative portions of one cycle of each of said two waveforms;

generating four digital values which are representative of the integrated portions, respectively, of said two waveforms;

establishing and storing reference digital values for the selected circuit node points;

comparing the generated digital values for each selected circuit node point with the corresponding reference digital values therefore; and

producing and displaying the analog signature obtained from those circuit node points which do not have a generated digital value within a selected range relative to said corresponding reference digital values.

10. A method of claim 9, wherein the reference digital values are obtained from an electronic circuit known to be good.

11. A method of claim 9, including the step of displaying the analog signatures which are not within the selected range following the complete testing of at least one integrated circuit, wherein the said signatures are displayed in order from most different to least different relative to the selected range.