Resilient bus system

• US 4,763,243 A
• Filed: 06/21/1984
• Issued: 08/09/1988
• Est. Priority Date: 06/21/1984
• Status: Expired due to Term

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Bull Incorporated (Atos SE)
• Inventors: Keeley, James W., Barlow, George J.
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US06/623,264
• Time in Patent Office: 1,510 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/107
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 13/4213 with asynchronous protocol

Abstract

A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and checking apparatus for verifying that all of the parts of a request received from such unit over the bus are valid. When less than all of the parts of the request are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.

Claims

1. A system including a plurality of units coupled in common to a system bus for transferring requests between said plurality of units during different allocated bus cycles of operation, each request being transferred during a number of said allocated bus cycles of operation, said system further including:

means included in at least one of said plurality of units for generating requests on said bus, each request containing a number of different parts, said parts each containing a number of integrity bits for verifying when said request is validly received by another unit of said plurality of units designated by said request during each of said number of allocated bus cycles of operation and at least one of said parts being coded to specify an operation to be performed by said another unit;

checking means included in said another unit, said checking means being coupled to said bus for verifying during each allocated bus cycle of operation that all of said number of different parts of said each request received from said bus by said checking means of said another unit are valid;

response means included in said another unit, said response means being coupled to said checking means and to said bus, said response means being inhibited by said checking means from generating any response on said bus to said one unit signalling acceptance of said request when said checking means verifies that less than all of said parts of said received request received during said each allocated bus cycle of operation are valid; and

,

means for accepting said request, said means for accepting being coupled to said bus and to said response means, said means for accepting being enabled to accept said request from said bus during each of said allocated bus cycles of operation upon said response means signalling said acceptance of said request and said means for accepting, rejecting said request applied to said bus during each of said allocated bus cycles of operation when said response means is inhibited from generating any response on said bus thereby ensuring that said another unit does not attempt to perform any operation specified by an invalid request.

2. The system of claim 1 wherein said system further includes timeout means coupled to said system bus, said timeout means being operative in the absence of any response from said another unit to generate a predetermined signal on said bus after a predetermined period of time indicating that said another unit has not accepted said request and said one unit further including retry means coupled to said system bus, said retry means in response to said signal causing said generating means to retry said request on said system bus during a subsequent bus cycle of operation.

3. The system of claim 2 wherein said one unit further includes indicator means coupled to said bus and to said retry means, said retry means causing said indicator means in response to said predetermined signal from said bus to generate a first error signal signifying to said one unit the occurrence of a first retry operation.

4. The system of claim 3 wherein said one unit further includes error means coupled to said indicator means and to said retry means, said indicator means causing said error means in response to a second occurrence of said predetermined signal to generate a second error signal signifying that said first retry operation performed by said retry means was unsuccessful and that further processing of said request is to be aborted by said one unit.

5. The system of claim 1 wherein said system bus includes a plurality of lines which are grouped into a plurality of groups, each group being arranged for receiving at least one predetermined part including at least one of said number of integrity bits of each said request during each of a number of bus cycles of operation.

6. The system of claim 5 wherein said plurality of groups include a multibit address bus group, a multibit data bus group and a multibit command bus group for receiving address, data and command bits respectively including said number of integrity bits of each request during each of said number of bus cycles of operation.

7. A system including a plurality of units of new and old designs coupled in common to a system bus for transferring requests between designated ones of said plurality of units during different asynchronously generated bus cycles of operation, said system further including:

first means included in at least a first unit of said plurality of units of said new design for generating requests on said bus, each request containing a number of different parts, each of said parts containing at least one integrity bit for verifying that said request is validly received by a second cycle of operation;

said system bus including a new parity line coupled only to each of said units of new design;

second means included in said first unit of said new design for applying a predetermined signal to said new parity line which identifies to a second one of said plurality of units said new design receiving said request that said request includes all integrity bits required for verifying that all of said number of parts of said request are valid;

checking means included in each of said plurality of units of said new design, said checking means of each of said units of new design being coupled to said new parity line and operative in response to said predetermined signal to verify that all of said number of different parts of said request designating said unit received from said bus by said unit are valid; and

,

response means included in each of said plurality of units of said new design and in each of said units of said old design, said response means of each of said units of said new design being coupled to said checking means associated therewith and to said bus, said response means of each of said units of said new design when designated by said request being inhibited by said checking means from generating any response to said request on said bus to said first unit when less than all of said parts of said received request are valid and said response means of each of said units of said old designs when designated by said request generating a response on said bus to said first unit subsequent to receiving said request in the same manner as said response would have been generated in a system which included only units of said old design.

8. The system of claim 7 wherein said checking means of each unit of said new design is operative in the absence of said predetermined signal to perform a checking operation on less than all of said parts of said received request and said response means of said each unit of said new design being conditioned by said checking means as a result of such checking operation to generate a type of acknowledgement response to one of said units of said old design which transmitted said received request, which is the same as would have been generated in a system, which included only said units of said old design.

9. The system of claim 7 wherein said response means of each unit of said new design is conditioned by said checking means when all of said parts of said received request are valid to generate a predetermined response to said first unit of said new design signalling that said request has been validly received.

10. The system of claim 9 wherein each of said units of said new design include connector means for applying said number of said integrity bits to said bus in a predetermined manner for enabling each of said units of said old design coupled to said bus to disregard said integrity bits and perform a check only those parts of said received request verified in said system designed to include only units of said old design.

11. The system of claim 7 wherein said system further includes timeout means coupled to said system bus, said timeout means being operative in the absence of any respnse from said another unit to generate a predetermined signal on said bus after a predetermined period of time indicating that said another unit has not accepted said request and said first unit further including retry means coupled to said system bus, said retry means in response to said signal causing said generating means to retry said request on said system bus during a subsequent bus cycle of operation.

12. The system of claim 11 wherein said first unit of said new design further includes indicator means coupled to said retry means, said retry means causing said indicator means in response to said predetermined signal from said bus to generate a first error signal signifying to said one unit the performance of a first retry operation.

13. The system of claim 12 wherein said first unit of said new design further includes error means coupled to said indicator means and said retry means, said indicator means causing said error means in response to a second occurrence of said predetermined signal to generate a second error signal signifying that said first retry operation performed by said retry means was unsuccessful and that said request is to be aborted by said first unit.

14. The system of claim 7 wherein said system bus includes a plurality of lines which are grouped into a plurality of groups, each group being arranged for receiving at least one predetermined part including at least one of said number of integrity bits of each of said request during each of a number of bus cycles of operation.

15. The system of claim 14 wherein said plurality of groups include a multibit address bus group, a multibit data bus group and a multibit command bus group for receiving address, data and command bits respectively including said number of integrity bits of each request during each of said number of bus cycles of operation.

16. The system of claim 8 wherein said checking means includes means which generates integrity bits for all of said parts of said received requests during said checking operation and each unit of said new design further including a number of internal paths and transfer means coupled to said internal paths, to said checking means, to said new parity line and to said system bus, said transfer means being operative to transfer to said internal paths within said each unit of said new design, said integrity bits generated by said checking means for those parts of said request received from said unit of said old design which did not contain integrity bits for enabling subsequent internal checking.

17. A method of operating a bus system in a resilient manner when transferring requests during different allocated bus cycles of operation between a plurality of data handling units coupled in common to said bus system, each request being transferred during a number of said allocated bus cycles of operation, said method comprising the steps of:

(a) generating requests on said bus system by means included in at least one of said data handling units, said each request containing a number of different parts, said parts each containing a number of integrity bits for verifying when said request is validly received by another unit designated by said request of said plurality of units during each of said number of allocated bus cycles of operation and at least one of said parts being coded to specify an operation to be performed by said another unit;

(b) checking by checking means included in at least another one of said data handling units, to verify that all of said number of different parts of said each request received by said another data handling unit from said bus during each allocated bus cycle of operation are valid;

(c) generating a response on said bus by response means included in said another one of said data handling units when enabled by said checking means;

(d) enabling said response means for generating a response on said bus only when all of said parts of said request received during said each allocated bus cycle of operation are signalled by said checking means as being valid;

accepting said request from said bus during each allocated bus cycle of operation when a response is generated signalling the receipt of a valid request; and

,

rejecting the request applied to said bus during each allocated bus cycle of operation when no response is generated signalling the receipt of an invalid request thereby ensuring that said another one of said data handling units does not attempt to perform any operation specified by an invalid request.

18. The method of claim 17 wherein said method further includes the steps of:

(d) generating a signal by timeout means connected to said bus system in the absence of said response for signalling to the unit which transmitted a request the occurrence of a bad bus cycle of operation in which the said designated receiving unit had not accepted the request because it was invalid; and

,

(e) retrying said request on said bus during another allocated bus cycle of operation by retry means included within such transmitting unit and which couples to said bus system.

19. The method of claim 17 wherein said method of operating said resilient bus system further includes the steps of:

generating a predetermined signal on a new parity line included in said bus system by each unit of a new design when said data handling units include both units of an old design and said new design for signalling when said number of said integrity bits is sufficient for verifying that all of said number of different parts of said each request applied to said bus is valid; and

,

applying said predetermined signal on said new parity line only as an input to the checking means of each unit of said new design.

20. The method of claim 17 wherein said method further includes the step of assigning said one and said another one of said data handling units the same channel number for enabling said unit to transfer requests to itself during said number of allocated bus cycles of operation in said resilient manner.