Bus device for use in a computer system having a synchronous bus

• US 4,763,249 A
• Filed: 10/29/1986
• Issued: 08/09/1988
• Est. Priority Date: 09/22/1983
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Bomba, Frank C., Jenkins, Stephen R., Binder, Paul, Schumann, Reinhard
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US06/924,578
• Time in Patent Office: 650 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 713/600
• CPC Class Codes: G06F 13/374 using a self-select method with individual priority code comparator

Abstract

A bus device is provided for use in a data processing system which includes a plurality of bus devices interconnected by a synchronous bus. The bus includes multiplexed data/address/arbitration lines which carry data, address, and arbitration information during respective data, command/address, and arbitration cycles. The bus also includes a BUSY line and a NO ARB line for controlling access to the data/address/arbitration lines. Where constructed as a memory device, the bus device includes memory circuits having a plurality of storage locations, and an interconnecting circuit which monitors the BUSY and NO ARB lines to identify various types of cycles on the bus, and which controls transmission of signals from the memory device over the bus in accordance with information derived by the monitoring means from the BUSY and NO ARB lines.

Claims

1. A method for transmitting stored data to and from a memory device in a data processing system that includes a plurality of bus devices and a common synchronous communications path for conducting signals thereon, the path including a plurality of command lines, a plurality of data/address lines, a NO ARB line precluding access to the data/address lines during the next cycle for purposes of arbitration when asserted, a BUSY line for indicating that a transaction is in progress during the next cycle when asserted, and at least one timing line for carrying timing signals defining timing cycles, the memory device being connected to the communciations path to operate in cycles in accordance with the timing signals on the timing line and including a plurality of storage locations each associated with a separate bus address, the method comprising:

a first step of monitoring the BUSY and NO ARB lines to detect a cycle in which the BUSY line is asserted and that immediately follows a cycle in which the BUSY line was unasserted and the NO ARB line was asserted, such cycle being denominated a command/address cycle;

a second step of monitoring the command and data/address lines during the command/address cycle to detect one of a read and a write command on the command lines and to detect signals on the data/address lines representing a bus address with which a storage location is associated; and

a third step of exchanging data between the memory device and another device over the data/address lines on the communications path during a data cycle which is the second cycle after the command/address cycle during which a bus address with which a storage location is associated has been detected on the data/address lines, and during which one of the read and write commands has been detected on the command lines.

2. A method as recited in claim 1 wherein the communications path additionally comprises a set of confirmation lines for carrying an ACK response to indicate correct receipt of commands by the memory device having storage locations associated with the bus address detected during the command/address cycle, the method comprising the additional step of the memory device asserting the ACK response during the same cycle in which the third step is executed.

3. A memory device for use in data processing system that includes a plurality of bus devices and a common synchronous communications path for conducting signals between the bus devices during transactions, the path including at least one timing line for carrying timing signals operating the memory device according to communications path timing cycles;

a plurality of command lines for carrying command signals including read and write commands during cycles designated as command/address cycles of read and write transactions;

a plurality of data/address/arbitration lines for carrying different types of information at different times, the data/address/arbitration lines carrying bus addresses of storage locations during command/address cycles of read and write transactions, carrying data during cycles designated as data cycles of read and write transactions, and carrying arbitration signals during cycles designated as arbitration cycles;

a NO ARB line precluding access to the data/address/arbitration lines during the next cycle for purposes of arbitration when asserted; and

a BUSY line for indicating that a transaction is in progress during the next cycle when asserted;

the memory device comprising;

memory means having a plurality of storage locations each associated with separate bus address for storing data; and

interconnecting means coupled to the memory means including means for monitoring the BUSY and NO ARB lines to detect a cycle in which the BUSY line is asserted that immediately follows a cycle in which the BUSY line was unasserted and the NO ARB line was asserted, such cycle being detected as the command/address cycle;

said interconnecting means controlling the transmission of data over the data/address/arbitration lines during the data cycle of read and write transactions for respectively retrieving data from and storing data in the storage locations, the data cycle being defined as a cycle which is the second cycle after a cycle;

(1) that the monitoring means has detected as a command/address cycle,

(2) during which a bus address with which one of the storage locations is associated is present on the data/address/arbitration lines; and

(3) during which one of the read and write commands is present on the command lines.

4. A memory device for use in a data processing system that includes a plurality of bus devices and a common synchronous communcations path for conducting signals between the bus devices during transactions, the path including at least one timing line for carrying timing signals operating the memory device according to communications path timing cycles;

a plurality of command lines for carrying command signals including read and write commands during cycles designated as command/address cycles of read and write transactions;

a plurality of data/address/arbitration lines for carrying different types of information at different times, the data/address/arbitration lines carrying bus addresses of storage locations during command/address cycles of read and write transactions, carrying data during cycles designated as data cycles of read and write transactions, and carrying arbitration signals during cycles designated as arbitration cycles;

a NO ARB line precluding access to the data/address/arbitration lines during the next cycle for purposes of arbitration when asserted;

a BUSY line for indicating that a transaction is in progress during the next cycle when asserted; and

a set of confirmation lines for carrying an ACK response to indicate correct receipt of read and write commands by the bus device having storage locations associated with the bus address carried during the command/address cycle;

the memory device comprising;

memory means for initiating an ACK response to indicate correct receipt of read and write commands, and having a plurality of storage locations each associated with separate bus addresses for storing data; and

interconnecting means coupled to the memory means including means for monitoring the BUSY and NO ARB lines to detect a cycle in which the BUSY line is asserted and that immediately follows a cycle in which the BUSY line was unasserted and the NO ARB line was asserted, such cycle being detected as the command/address cycle;

said interconnecting means controlling the transmission of an ACK response initiated by the memory means over the confirmation lines during the data cycle, and controlling transfer of data over the data/address/arbitration lines during the data cycle of read and write transactions for respectively retrieving data from and storing data in the storage locations, the data cycle being defined as the second cycle after a cycle;

(1) that the monitoring means has detected as a command/address cycle,

(2) during which a bus address with which one of the storage locations is associated is present on the data/address/arbitration lines; and

(3) during which one of the read and write commands is present on the command lines.

5. A mass storage device for use in a data processing system that includes a plurality of bus devices and a common synchronous communications path for conducting signals between the bus devices during transactions, the path including at least one timing line for carrying timing signals operating the mass storage device according to communications path timing cycles;

a plurality of command lines for carrying command signals including read and write commands during cycles designated as command/address cycles of read and write transactions;

a plurality of data/address/arbitration lines for carrying different types of information at different times, the data/address/arbitration lines carrying bus addresses of storage locations during command/address cycles of read and write transactions, carrying data during cycles designated as data cycles of read and write transactions, and carrying arbitration signals during cycles designated as arbitration cycles;

a NO ARB line precluding access to the data/address/arbitration lines during the next cycle for purposes of arbitration when asserted; and

a BUSY line for indicating that a transaction is in progress during the next cycle when asserted;

the mass storage device comprising;

memory means having a plurality of storage locations each associated with separate bus addresses for storing data; and

interconnecting means coupled to the memory means including means for monitoring the BUSY and NO ARB lines to detect a cycle in which the BUSY line is asserted that immediately follows a cycle in which the BUSY line was unasserted and the NO ARB line was asserted, such cycle being detected as the command/address cycle;

said interconnecting means controlling the transmission of data over the data/address/arbitration lines during the data cycle of read and write transactions for respectively retrieving data from and storing data in the storage locations, the data cycle being defined as a cycle which is the second cycle after a cycle;

(1) that the monitoring means has detected as a command/address cycle,

(2) during which a bus address with which one of the storage locations is associated is present on the data/address/arbitration lines; and

(3) during which one of the read and write commands is present on the command lines.

6. A mass storage device for use in a data processing system that includes a plurality of bus devices and a common synchronous communications path for conducting signals between the bus devices during transactions, the path including at least one timing line for carrying timing signals operating the mass storage device according to communications path timing cycles;

a plurality of command lines for carrying command signals including read and write commands during cycles designated as command/address cycles of read and write transactions;

a plurality of data/address/arbitration lines for carrying different types of information at different times, the data/address/arbitration lines carrying bus addresses of storage locations during command/address cycles of read and write transactions, carrying data during cycles designated as data cycles of read and write transactions, and carrying arbitration signals during cycles designated as arbitration cycles;

a NO ARB line precluding access to the data/address/arbitration lines during the next cycle for purposes of arbitration when asserted; and

a BUSY line for indicating that a transaction is in progress during the next cycle when asserted; and

a set of confirmation lines for carrying an ACK response to indicate correct receipt of read and write commands by the bus device having storage locations associated with the bus address carried during the command/address cycle;

the mass storage device comprising;

memory means for initiateng an ACK response to indicate correct receipt of read and write commands, and having a plurality of storage locations each associated with separate bus addresses for storing data; and

interconnecting means coupled to the memory means including means for monitoring the BUSY and NO ARB lines to detect a cycle in which the BUSY line is asserted and that immediately follows a cycle in which the BUSY line was unasserted and the NO ARB line was asserted, such cycle being detected as the command/address cycle;

said interconnecting means controlling the transmission of an ACK response initiated by the memory means over the confirmation lines during the data cycle, and controlling transfer of data over the data/address/arbitration lines during the data cycle of read and write transactions for respectively retrieving data from and storing data in the storage locations, the data cycle being defined as the second cycle after a cycle;

(1) that the monitoring means has detected as a command/address cycle,

(2) during which a bus address with which one of the storage locations is associated is present on the data/address/arbitation lines; and

(3) during which one of the read and write commands is present on the command lines.

7. A bus device for use in a data processing system that includes a plurality of bus devices and a common synchronous communications path for conducting signals between the bus devices during transactions, the path including at least one timing line for carrying timing signals operating the bus device according to communications path timing cycles;

a plurality of command lines for carrying command signals including read and write commands during cycles designated as command/address cycles of read and write transaction;

a plurality of data/address/arbitration lines for carrying different types of information at different times, the data/address/arbitration lines carrying bus addresses of storage locations during command/address cycles of read and write transactions, carrying data during cycles designated as data cycles of read and write transactions, and carrying arbitration signals during cycles designated as arbitration cycles;

a NO ARB line precluding access to the data/address/arbitration lines during the next cycle for purposes of arbitration when asserted; and

a BUSY line for indicating that a transaction is in progress during the next cycle when asserted;

the bus device comprising;

memory means having a plurlity of storage locations each associated with separate bus addresses for storing data; and

interconnecting means coupled to the memory means including means for monitoring the BUSY and NO ARB lines to detect a cycle in which the BUSY line is asserted that immediately follows a cycle in which the BUSY line was unasserted and the NO ARB line was asserted, such cycle being detected as the command/address cycle;

said interconnecting means controlling the transmission of data over the data/address/arbitration lines during the data cycle of read and write transactions for respectively retrieving data from and storing data in the storage locations, the data cycle being defined as a cycle which is the second cycle after a cycle;

(1) that the monitoring means has detected as a command/address cycle,

(2) during which a bus address with which one of the storage locations is associated is present on the data/address/arbitation lines; and

(3) during which one of the read and write commands is present on the command lines.

8. A bus device for use in a data processing system that includes a plurality of bus devices and a common synchronous communications path for conducting signals between the bus devices during transactions, the path including at least one timing line for carrying timing signals operating the bus device according to communications path timing cycles;

a plurality of command lines for carrying command signals including read and write commands during cycles designated as command/address cycles of read and write transaction;

a plurality of data/address/arbitration lines for carrying different types of information at different times, the data/address/arbitration lines carrying bus addresses of storage locations during command/address cycles of read and write transactions, carrying data during cycles designated as data cycles of read and write transactions, and carrying arbitration signals during cycles designated as arbitration cycles;

a NO ARB line precluding access to the data/address/arbitration lines during the next cycle for purposes of arbitration when asserted; and

a BUSY line for indicating that a transaction is in progress during the next cycle when asserted; and

a set of confirmation lines for carrying an ACK response to indicate correct receipt of read and write commands by the bus device having storage locations associated with the bus address carried during the command/address cycle;

the bus device comprising;

memory means for initiating an ACK response to indicate correct receipt of read and write commands, and having a plurality of storage locations each associated with separate bus addresses for storing data; and

interconnecting means coupled to the memory means including means for monitoring the BUSY and NO ARB lines to detect a cycle in which the BUSY line is asserted and that immediately follows a cycle in which the BUSY line was unasserted and the NO ARB line was asserted, such cycle being detected as the command/address cycle;

said interconnecting means controlling the transmission of an ACK response initiated by the memory means over the confirmation lines during the data cycle, and controlling transfer of data over the data/address/arbitration lines during the data cycle of read and write transactions for respectively retrieving data from and storing data in the storage locations, the data cycle being defined as the second cycle after a cycle;

(1) that the monitoring means has detected as a command/address cycle,

(2) during which a bus address with which one of the storage locations is associated is present on the data/address/arbitation lines; and

(3) during which one of the read and write commands is present on the command lines.