High density electronic package comprising stacked sub-modules

• US 4,764,846 A
• Filed: 01/05/1987
• Issued: 08/16/1988
• Est. Priority Date: 01/05/1987
• Status: Expired due to Term

• Current Assignee: Irvine Sensors Corp.
• Original Assignee: Irvine Sensors Corp.
• Inventors: Go, Tiong C.
• Primary Examiner(s): Paschall, M. H.
• Assistant Examiner(s): THOMPSON, GREGORY D
• Application Number:
  US07/000,562
• Time in Patent Office: 589 Days
• Field of Search: 29/830, 29/840, 361/386-389, 361/392-394, 361/396, 361/414
• US Class Current: 361/708
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/1627 stacked type assemblies, e.g. stacked multi-cavities
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10T 29/49126 Assembling bases

Abstract

A high density electronic package is disclosed in which a stack of layer-like sub-modules have their edges secured to a stack-carrying substrate, the latter being in a plane perpendicular to the planes in which the sub-modules extend. Each sub-module has a cavity, inside which one or more IC chips are located. Each cavity-providing sub-module may be formed either by securing a rectangular frame to a chip-carrying substrate, or by etching a cavity in a single piece of material. In the latter case, the chips are mounted on the flat surface of one sub-module, and located inside the cavity of the next sub-module.

Claims

1. A method of forming a high-density electronic package comprising:

forming a chip-carrying substrate which (a) has a metallization pattern thereon to provide electrical conductors extending to at least one conductor-providing edge of the substrate, and (b) provides a heat-conducting path to said edge of the substrate;

securing at least one IC chip to the chip-carrying substrate, such IC chip having electrical terminals thereon;

connecting the electrical terminals of the IC chip to the conductors on the chip-carrying substrate;

forming a spacer having a frame surrounding an open center portion;

securing the spacer to the chip-carrying substrate with the IC chip inside the open center portion;

the chip-carrying substrate, IC chip and spacer being a sub-module assembly;

securing together several of such sub-module assemblies to provide an integrated stack, containing several IC chips;

forming a stack-carrying substrate which (a) has a metallization pattern thereon to provide electrical conductors, and (b) provides a heat-conducting path;

integrating the stack of sub-module assemblies with the stack-carrying substrate by securing the conductor-providing edges of the chip-carrying substrates to the stack-carrying substrate in such a way as to (a) connect the conductors on the chip-carrying substrates to the conductors on the stack-carrying substrate, and (b) provide direct heat conduction from the edges of the chip-carrying substrates to the stack-carrying substrate.

2. The method of claim 1 in which the chip-carrying substrates and spacers are formed of material which is both electrically non-conductive and thermally conductive.

3. The method of claim 2 in which the material is beryllium oxide.

4. The method of claim 1 in which the dimensions of each spacer are such that, in each sub-module assembly, the conductor-providing edge of the chip-carrying substrate is located beyond the adjacent edge of the spacer, in order to provide an open space between the stack-carrying substrate and the spacer.

5. The method of claim 1 in which the chip-carrying substrates and spacers in the integrated stack are secured together in such a way as to provide a hermetic seal;

and

a cover is applied over the end spacer and hermetically sealed to it.

6. A high-density electronic package comprising:

a stack-carrying, heat-conducting substrate having conductors formed thereon;

a stack of sub-module assemblies extending in planes perpendicular to the stack-carrying substrate, and having edges secured to the stack-carrying substrate;

each sub-module assembly comprising;

(a) a chip-carrying, heat-conducting substrate having electrical conductors thereon, and having an edge secured to the stack-carrying substrate in such a way that heat is conducted from the chip-carrying substrate into the stackcarrying substrate;

(b) an IC chip mounted on the chip-carrying substrate and electrically connected to the conductors on that substrate; and

which the IC chip is located, and which is secured to the chip-carrying substrate;

each spacer determining the distance between adjacent chip-carrying substrates in the stack of sub-module assemblies; and

each chip-carrying substrate having its electrical conductors extending to the edge which is secured to the stack-carrying substrate and electrically connected to corresponding conductors on the stack-carrying substrate.

7. The electronic package of claim 6 in which the stack-carrying substrate, the chip-carrying substrates, and the spacers are all formed of electrically non-conducting material which has relatively high thermal conductivity.

8. The electronic package of claim 7 in which the material is beryllium oxide.

9. The electronic package of claim 6 in which the edges of the chip-carrying substrates which are secured to the stack carrying substrate extend beyond the adjacent edges of the spacers, in order to provide open spaces between the peripheries of the spacers and the stack-carrying substrate.

10. The electronic package of claim 6 in which the edge of each chip-carrying substrate is secured to the stack-carrying substrate by reflow soldering.

11. The electronic package of claim 6 in which the IC chips are gallium arsenide chips.

12. A high density electronic package containing IC chips, comprising:

a stack-carrying, heat-conducting substrate having electrical conductors formed thereon; and

a stack containing sub-modules extending in planes perpendicular to the stack-carrying substrate, and each having an edge secured to the stack-carrying substrate in such a way that heat is conducted from the sub-module into the stack-carrying substrate;

each sub-module having a heat-conducting, chip-carrying surface and a chip-surrounding cavity;

at least one IC chip mounted on the chip-carrying surface of each sub-module;

each chip-carrying surface having electrical conductors thereon which extend to the sub-module edge secured to the stack-carrying substrate, and which are electrically connected to corresponding conductors on the stack-carrying substrate.

13. The electronic package of claim 12 in which:

the chip-surrounding cavity in each sub-module is provided inside a single piece of material; and

the chip which is located inside the cavity of one sub-module is supported on the surface of the adjacent sub-module.

14. The electronic package of claim 13 in which the material of each sub-module is a heat-conducting ceramic material

the chip which is located inside the cavity of one sub-module is supported on the surface of the adjacent sub-module.

15. A method of forming a high-density electronic package containing IC chips, comprising:

forming a plurality of sub-modules, each having a chip-surrounding cavity and a heat-conducting chip-carrying surface;

providing electrical conductors on the chip-carrying surface of each sub-module;

mounting at least one chip on each chip-carrying surface and connecting it to the electrical conductors on that surface;

stacking and securing together a plurality of sub-modules;

providing a heat-conducting stack-carrying substrate having electrical conductors formed thereon; and

securing the stacked sub-modules to the stack-carrying substrate with each sub-module extending in a plane perpendicular to the stack-carrying substrate, with a direct heat-conducting path from each sub-module into the stack-carrying substrate electrically connected to the electrical conductors on the chip-carrying surface of the sub-modules;

each chip being located in a cavity of a sub-module.

16. The method of claim 15 in which each chip is mounted on the chip-carrying surface of one sub-module, and located inside a cavity of another sub-module.

17. The method of claim 16 which also comprises the step of:

etching a recess in a block of sub-module material to form a chip-surrounding cavity therein.

18. The method of claim 15 in which each chip is connected to the electrical conductors on its respective chip-carrying surface by the following process;

forming a non-metallic tape carrying a plurality of electrically-conducting fingers;

soldering in a single step one end of each finger to an electrical terminal on the chip; and

soldering in a single step the other end of each finger to one of the electrical conductors on the chip-carrying surface.