Resilient bus system

• US 4,764,862 A
• Filed: 03/28/1985
• Issued: 08/16/1988
• Est. Priority Date: 06/21/1984
• Status: Expired due to Fees

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Bull Incorporated
• Inventors: Keeley, James W., Barlow, George J.
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US06/717,201
• Time in Patent Office: 1,237 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 371/76
• US Class Current: 709/253
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 13/4213 with asynchronous protocol

Abstract

A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and like checking apparatus for verifying that the different parts of a request received from such unit over the bus are valid based upon the states of accompanying function identification signals. When less than all of the parts of the request defined as requiring verification are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.

Claims

1. A system including a plurality of units coupled in common to a system bus for transferring requests between said plurality of units during different bus cycles of operation, each request being transferred during a number of allocated bus cycles of operation, said system further including:

means included in at least one of said plurality of units for generating requests on said bus, each request containing a number of different parts, said parts each containing a number of integrity bits for verifying when different parts of said request are validly received by another unit of said plurality of units designated by request during each of said number of allocated bus cycles of operation and at least one of said parts being coded to specify an operation to be performed by said another unit;

checking means included in said another unit, said checking means being coupled to said bus for receiving and for verifying during each allocated bus cycle of operation that only those parts of said number of different parts of said each request designated by said one of said plurality of units received by said checking means of said another unit are valid;

response means included in said another unit, said response means being coupled to said checking means and to said bus, said response means being inhibited by said checking means from generating any response on said bus to said one unit during each allocated bus cycle of operation which signals the acceptance of said request when said checking means verifies that less than all of said designated parts of said received request are valid; and

,

means for accepting said request, said means for accepting being coupled to said bus and to said response means, said means for accepting being enabled to accept said request from said bus during each of said allocated bus cycles of operation upon said response means signalling said acceptance of said request and said means for accepting, rejecting said request applied to said bus during each of said allocated bus cycles of operation when said response means is inhibited from generating any response on said bus thereby ensuring that said another unit does not attempt to perform any operation specified by an invalid request.

2. The system of claim 1 wherein said system bus includes a plurality of function identification lines, each associated with at least one of said number of different parts of said each request, said function identification lines being set to states by said one of said plurality of units for designating those parts of said each request to be verified by said checking means of said another unit.

3. The system of claim 2 wherein each of said plurality of units include identical checking means which couple to said function identification lines of said system bus.

4. The system of claim 3 wherein said system bus further includes a number of exception lines for signalling the detection of uncorrectable error conditions, said number of said exception lines being coupled to each of said identical checking means, each of said identical checking means being conditioned by each of said number of exception lines to verify those predetermined parts of each request received from the unit associated therewith specified by the state of said each of said number of exception lines.

5. The system of claim 4 wherein said predetermined parts of said each request correspond to the data portion of said each request.

6. The system of claim 1 wherein said system further includes timeout means coupled to said system bus, said timeout means in the absence of any response from said another unit generating a predetermined signal on said bus after a predetermined period of time indicating that said another unit has not accepted said request and said one unit further including retry means coupled to said system bus, said retry means in response to said signal causing said generating means to retry said request on said system bus during a subsequent bus cycle of operation.

7. The system of claim 6 wherein said one unit further includes indicator means coupled to said retry means, said retry means causing said indicator means in response to said predetermined signal from said bus to generate a first error signal to said one unit signifying the occurrence of a first retry operation.

8. The system of claim 7 wherein said one unit further includes error means coupled to said indicator means and retry means, said indicator means causing said error means in response to a second occurrence of said predetermined signal to generate a second error signal signifying that said first retry operation performed by said retry means was unsuccessful and that further processing of said request is to be aborted by said one unit.

9. The system of claim 1 wherein said system bus includes a plurality of lines which are divided into a plurality of sections, each section being arranged for receiving at least one predetermined part including at least one of said number of integrity bits of each said request during each of a number of bus cycles of operation.

10. The system of claim 1 wherein said plurality of sections include a multibit address bus section, a multibit data bus section and a multibit command bus section for receiving address, data and command bits respectively including said number of integrity bits of each request during each of said number of bus cycles of operation.

11. A system including a plurality of units of new and old designs coupled in common to a system bus for transferring requests between said plurality of units during different asynchronously generated bus cycles of operation, said system further including:

first means included in at least a first unit of said plurality of units for generating requests on said bus, each request containing a number of different parts, each of said parts containing at least one integrity bit for verifying that said request is validly received by a second unit of said plurality of units of said new design during an allocated bus cycle of operation;

said system bus including;

a bus new parity line coupled only to each of said units of new design;

a bus new address line coupled only to each of said units of said new design; and

,

a number of exception lines coupled to each of said units of said new design and said old design;

second means included in said first unit of said new design for applying predetermined signals to said new parity line, to said new address line and to said number of exception lines for identifying to a second one of said plurality of units of said new design specified to receive said request which ones are to be verified of said number of parts of said request including integrity bits for verifying that all of said number of parts of said request are valid;

checking means included in each of said plurality of units of said new design, said checking means of each of said units of new design being coupled to said new parity line, to said new address line and to said number of exception lines, said checking means verifying as valid only those different parts of said request received from said bus by said checking means of said unit which are specified by said predetermined signals applied to said new parity line, said new address line and said number of exception lines by said first unit of said new design; and

,

response means included in each of said plurality of units of said new design, said response means being coupled to said checking means and to said bus, said response means of each of said units of said new design being inhibited by said checking means from generating any response on said bus to said first unit signifying acceptance of said request when less than those specified parts of said received request are valid.

12. The system of claim 11 wherein said checking means of each unit of said new design in the absence of each predetermined signal performs a checking operation on the remaining parts of said received request and said response means of said each unit of said new design being conditioned by said checking means as a result of such checking operation to generate a response to one of said units of said old design which transmitted said received request, said response being the same as that which would have been generated in a system which included only said units of said old design.

13. The system of claim 11 wherein said response means of each unit of said new design is conditioned by said checking means when all of those different parts of said received request specified by said predetermined signals are valid to generate a predetermined response to said first unit signalling that said request has been validly received.

14. The system of claim 13 wherein each of said units of said new design include connector means for applying said number of said integrity bits to said bus in a predetermined manner for enabling each of said units of said old design coupled to said bus to disregard said integrity bits and perform a check only on those parts of said received request which are verified in said system including only said units of said old design.

15. The system of claim 11 wherein said system further includes timeout means coupled to said system bus, said timeout means in the absence of any response from said another unit generating a predetermined signal on said bus after a predetermined period of time indicating that said another unit has not accepted said request and said one unit further including retry means coupled to said system bus, said retry means in response to said signal causing said generating means to retry said request on said system bus during a subsequent bus cycle of operation.

16. The system of claim 15 wherein said one unit further includes indicator means coupled to said retry means, said retry means causing said indicator means in response to said predetermined signal from said bus to generate a first error signal to said one unit signifying the occurrence of a first retry operation.

17. The system of claim 13 wherein said one unit further includes error means coupled to said indicator means and said retry means, said indicator means causing said error means in response to a second occurrence of said predetermined signal to generate a second error signal signifying that said first retry operation performed by said retry means was unsuccessful and that further processing of said request is to be aborted by said one unit.

18. The system of claim 11 wherein said system bus includes a plurality of lines which are divided into a plurality of sections, each section being arranged for receiving at least one predetermined part including at least one of said number of integrity bits of each of said request during each of a number of bus cycles of operation.

19. The system of claim 11 wherein said plurality of sections include a multibit address bus section, a multibit data bus section and a multibit command bus section for receiving address, data and command bits, respectively, including said number of integrity bits of each request during each of said number of bus cycles of operation.

20. The system of claim 12 wherein said checking means generates integrity bits for all of said parts of said received requests and each unit of said new design further including a number of internal paths and transfer means coupled to said internal paths, to said checking means to said new parity line, to said new address line and to said system bus, said transfer means being operative to transfer to said internal paths within said each unit of said new design, integrity bits generated by said checking means for those parts of said request received and accepted from said unit of said old design which did not contain integrity bits.

21. A method of operating a bus system in a resilient manner when transferring requests during different allocated bus cycles of operation between a plurality of data handling units coupled in common to said bus system, each request being transferred during a number of said allocated bus cycles of operation, said method comprising the steps of:

(a) partitioning each request into a number of different parts;

(b) generating requests on said bus system by means included in at least one of said units in which each part contains a number of integrity bits for verifying when said request is validly received by another unit of said plurality of units designated by said request during each of said number of allocated bus cycles of operation and at least one of said parts being coded to specify an operation to be performed by said another unit;

(c) generating signals on a number of function identification lines included in said bus system for specifying which ones of said number of different parts of said each request are to be verified during normal and testing operations during an allocated bus cycle of operation;

(d) checking by checking means included in at least another one of said data handling units only those different parts of said request designated by said number of function identification lines for verifying that said request received by said checking means of said another data handling unit during said each allocated bus cycle of operation is valid; and

,

(e) generating a response on said bus by response means included in said another one of said units only when all of said designated parts of said request received during said each allocated bus cycle of operation are signalled by said checking means as being valid; and

,

accepting said request from said bus during each allocated bus cycle of operation when a response is generated signalling the receipt of a valid request; and

,

rejecting the request applied to said bus during each allocated bus cycle of operation when no response is generated signalling the receipt of an invalid request thereby ensuring that said another one of said data handling units does not attempt to perform any operation specified by an invalid request.

22. The method of claim 21 wherein said method further includes the steps of:

(f) generating a signal by timeout means connected to said bus system in the absence of said response for signalling to the unit which transmitted a request, the occurrence of a bad bus cycle of operation in which the intended receiving unit had not accepted the request because it was invalid; and

,

(g) retrying said request on said bus system during another allocated bus cycle of operation by retry means including within such transmitting unit.

23. The method of claim 21 wherein said step of generating signals on a number of said function identification lines includes the steps of:

generating predetermined signals on a new parity line and a new address line included in said bus system when said data handling units include units of old and new designs; and

,

applying said predetermined signals on said new parity line and said new address line only as inputs to the checking means of each unit of a new design.

24. The method of claim 21 wherein said method further includes the step of assigning said one and said another one of said data handling units the same channel number for enabling said unit to transfer requests to itself in said resilient manner.