Method and apparatus for testing integrated circuits

• US 4,764,925 A
• Filed: 06/14/1984
• Issued: 08/16/1988
• Est. Priority Date: 06/14/1984
• Status: Expired due to Fees

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: Fairchild Camera and Instrument Corporation (ON Semiconductor Corporation)
• Inventors: Grimes, Scott D., Reed, Douglas A., Beaulieu, Lary J.
• Primary Examiner(s): Fleming, Michael R.
• Application Number:
  US06/620,736
• Time in Patent Office: 1,524 Days
• Field of Search: 364/900, 364/200, 371/16, 371/20, 371/27, 371/25, 371/21, 371/15, 324/73 R, 324/73 AT, 324/73 PC
• US Class Current: 714/743
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

A processor controlled IC component test apparatus adapted to be employed in-line with automatic IC DIP component handling equipment is capable of conducting a preselected verification check of each IC device regardless of the orientation of the DIP in the device contact receptable of the IC handling apparatus. As each device under test (DUT) is inserted into the apparatus test head, a pin-check residual voltage measurement test is conducted to ensure that all the pins of the DUT are in contact with the contact terminals of the test head. If the pin-check test establishes that all the pins of the DUT are in contact with the contact terminals of the test head, a prescribed non-destructive impedance measurement test is carried out in order to determine the orientation of the DIP in the test head. If the device passes the orientation test or is determined by the orientation test to be simply misoriented (inserted upside-down), it is then subjected to a prescribed functionality check (with the direction of orientation taken into account).

The processor architecture of the test apparatus is configured to maximize the systems'"'"'s ability to rapidly sequence through the test vectors for the various DUTs, while also offering the capability to perform traditional CPU functions during the execution of a test. For this purpose, the processor employs a mode-controlled pipelined architecture through which program instructions stored in memory are controllably accessed and processed through either an address-controlled flow path or a data-controlled flow path.

Claims

1. An apparatus for testing a circuit device, said circuit device having a plurality of terminal pins through which said device is adapted to be operated in accordance with its intended circuit function, comprising:

first means for generating a sequence of test control signals in accordance with which a circuit device is tested;

a plurality of second means, each of which second means is associated with a respective one of said terminal pins and stores a plurality of electrical stimulas-representative signals for causing the selective application of electrical stimulas signals to said associated respective one of said terminal pins in response to a test control signal generated by said first means, and sensor means, adapted to be coupled to said associated respective one of said terminal pins, for monitoring a prescribed electrical parameter thereat; and

control means for selectively altering said sequence of test control signals in response to an electrical parameter monitored by one of said sensor means.

2. An apparatus according to claim 1, wherein said first means includes memory means in which a series of test control instructions are stored, and said control means comprises address generator means, responsive to a test control instruction in said memory means, for generating a test control signal as an address signal for accessing a test control instruction from said memory means and for accessing a respective electrical stimulas-respective signal for each of said plurality of second means for application to the terminal pins of said circuit device.

3. An apparatus according to claim 2, wherein said address generator means is adapted to be responsive to prescribed outputs of said sensor means in the course of the generation of a test control signal as said address signal.

4. An apparatus according to claim 2, wherein said series of test control instructions stored by said memory means includes first prescribed test control instructions in response to successive ones of which said address generator means is adapted to generate successive test control signals for both addressing that portion of said memory means containing said first prescribed test control instructions and accessing from said second means said electrical stimulus-representative signals.

5. An apparatus according to claim 4, wherein each of said second means includes a terminal pin test control memory adapted to store a plurality of said electrical stimulus-representative signals in respective memory locations thereof, said memory locations being addressable by the address representative test control signals generated by said address generator means.

6. An apparatus according to claim 4, wherein said first means is adapted to be coupled with data processing means, and said series of test control instructions stored by said memory means includes second prescribed test control instructions associated with prescribed data processing operations to be conducted by said data processing means, in response to which data processing operations the addresses of further test control instructions to be accessed from said memory means are defined.

7. An apparatus according to claim 6, wherein said first means further includes means, responsive to the generation of an address signal for accessing one of said second prescribed test control instructions from said memory means, for storing the most recent address representative test control signal generated by said address generator means that defined a memory location in said memory means in which one of said first prescribed test control instructions is stored.

8. An apparatus according to claim 1, wherein each of said second means includes driver circuit means, responsive to said electrical stimulus-representative signals, for controllably generating electrical stimulus signals for application to its associated terminal pin.

9. An apparatus according to claim 8, wherein each of said second means further includes means for establishing the levels of like electrical stimulus signals generated by the driver circuit means of every one of said second means irrespective of differences in inherent electrical characteristics among the driver circuit means.

10. An apparatus according to claim 9, wherein each of said second means includes sensor means, adopted to be coupled to said associated respective one of said terminal pins, for monitoring a prescribed electrical parameter thereat.

11. An apparatus according to claim 10, wherein said establishing means includes means for coupling a varying electrical input to each of said driver circuit means and, in response to the output of said sensor means reaching a prescribed level of one of said like electrical stimulus signals, for storing a signal corresponding to the value of said varying electrical signal for which the output of said sensor means reached said prescribed level.

12. An apparatus according to claim 8, wherein said second means further includes output switch means, coupled to the output of said driver circuit means, for selectively coupling the output of said driver circuit means to its associated terminal pin of said circuit device.

13. An apparatus according to claim 12, wherein said output switch means comprises an MOS transistor the source-drain path of which is coupled between the output of said driver circuit means and said associated terminal pin, and the gate of which is coupled to the output of said driver circuit means.

14. An apparatus according to claim 13, wherein said output switch means further include means, coupled between the gate of said MOS transistor and the output of said driver circuit means, for limiting the voltage coupled said gate relative to the voltage at the output of said driver circuit means.

15. For use with an apparatus for generating electrical stimulas signals to be coupled to an output circuit device, a processor-controlled arrangement for controlling the accessing of instructions from memory, through prescribed operations on which instructions said electrical stimulas signals are generated, comprising:

first means, adapted to be coupled to said output circuit, and comprising a plurality of driver memory means each storing a respective plurality of said electrical stimulas-representative signals for causing the selective application of electrical stimulas signals to said output circuit device; and

second means, including a memory unit and responsive to the contents of instructions stored therein, for generating storage access signals and causing said storage access signals to be coupled to both said memory unit for accessing instructions therefrom and to said first means for accessing electrical stimulas-representative signals therefrom for a first mode of operation of said processor, and for generating address signals for accessing instructions from said memory unit that are associated with prescribed data processing operations of said processor, in response to which processing operations the addresses of further instructions to be accessed from said memory unit are defined, for a second mode of operation of said processor.

16. A processor-controlled arrangement according to claim 15, wherein said second means includes means, responsive to said second mode of operation of said processor, for storing the most recent storage access signal generated during said first mode of operation of said processor.

17. A processor-controlled arrangement according to claim 15, wherein each storage access signal generated by said second means is applied in common to each of said memory means.

18. A processor-controlled arrangement according to claim 17, wherein said output circuit device comprises a multiterminal circuit device to the respective terminals of which said electrical stimulus signals are applied for testing said output circuit device.