Digital frame synchronizer

• US 4,764,941 A
• Filed: 05/22/1987
• Issued: 08/16/1988
• Est. Priority Date: 05/22/1987
• Status: Expired due to Term

• Current Assignee: American Telephone & Telegraph Company (AT&T, Inc.), Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: American Telephone & Telegraph Company (AT&T, Inc.)
• Inventors: Choi, DooWhan
• Primary Examiner(s): Leung, Philip H.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/053,284
• Time in Patent Office: 452 Days
• Field of Search: 375/106, 375/111, 375/112, 375/118, 375/119, 370/102
• US Class Current: 375/363
• CPC Class Codes: H04J 3/076 Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Abstract

A desired positive fractional stuffing ratio is obtained in a frame synchronizer for a digital signal having a channel frame format that included two stuffing bit positions to obtain either positive or negative stuffing. The fractional stuffing ratio is obtained by controllably increasing the duration of a first predetermined number of intervals during which data bits are written into the synchronizer and, then, by controllably decreasing the duration of a second predetermined number of intervals during which data bits are written into the synchronizer. A data bit is forced to be included in one of the stuffing bit positions occurring during each of the first predetermined number of intervals and a non-data bit is forced to be included in one of the stuffing bit positions occurring during each of the second predetermined number of intervals.

Claims

1. A synchronizer in which digital signals at a first transmission bit rate are synchronized by use of bit stuffing to a second higher transmission bit rate for transmission in an output frame format, comprising,

means for obtaining a predetermined fractional stuffing ratio for output frames from said synchronizer, said means for obtaining including means for controllably varying in a prescribed manner intervals during which data bits are being inputted into said synchronizer, wherein a fractional stuffing ratio is obtained.

2. The synchronizer as defined in claim 1 wherein said means for varying includes means for increasing in a first prescribed manner the duration of a first predetermined number of intervals during which data bits are being inputted into said synchronizer.

3. The synchronizer as defined in claim 2 wherein said means for varying further includes means for decreasing in a second prescribed manner the duration of a second predetermined number of intervals during which data bits are being inputted into said synchronizer.

4. The synchronizer as defined in claim 3 wherein said means for obtaining further includes means for adjusting the data transport capacity of output framers from said synchronizer.

5. The synchronizer as defined in claim 4 wherein said means for adjusting includes means for inserting a data bit in a predetermined one of stuffing bit positions occurring during each of said first predetermined number of intervals.

6. The synchronizer as defined in claim 5 wherein said means for adjusting further includes means for inserting a non-data bit in a predetermined one of stuffing bit positions occurring during each of said second predetermined number of intervals.

7. The synchronizer as defined in claim 6 wherein said intervals are frame intervals and said first predetermined number of intervals and said second predetermined number of intervals form a multi-frame having a predetermined total number of frames equal to the sum of said first and second predetermined numbers.

8. The synchronizer as defined in claim 7 wherein said fractional stuffing ratio is obtained for said multi-frame and is equal to said first predetermined number divided by said predetermined total number.

9. A synchronizer in which digital signals at a first transmission bit rate are synchronized by use of bit stuffing to a second higher transmission bit rate for transmission in an output frame format, comprising,

an asynchronous stuffing stage for generating intermediate frames,

means associated with said asynchronous stuffing stage for controllably increasing the nominal number of incoming data bits accommodated for a first predetermined number of said intermediate frames and for controllably decreasing the nominal number of incoming data bits accommodated for a second predetermined number of said intermediate frames, and

a synchronous stuffing stage supplied with said intermediate frames for generating output frames each having a predetermined number of bits, wherein a fractional stuffing ratio is obtained.

10. The synchronizer as defined in claim 9 wherein said means for controllably increasing and decreasing includes means for inserting a data bit in a stuffing bit position in said first predetermined number of intermediate frames and means for eliminating a stuffing bit position from said second predetermined number of intermediate frames.

11. The synchronizer of claim 10 wherein said first and second predetermined number of frames form an intermediate multi-frame having a total number of intermediate frames equal to the sum of said first and second predetermined numbers.

12. The synchronizer of claim 11 wherein an output clock rate having a first predetermined rate is employed to read bits out of said synchronous stuffing stage and an intermediate clock rate having a second predetermined rate which is less than and in prescribed relationship to said first predetermined bit rate is used to read bits out of said asynchronous stuffing stage.

13. The synchronizer as defined in claim 12 further including means associated with said synchronous stuffing stage for controllably inserting a non-data bit into the eliminated stuffing bit position in said second predetermined number of intermediate frames to form said output frames.

14. A synchronizer in which digital signals at a first transmission bit rate are synchronized by use of bit stuffing to a second higher transmission bit rate for transmission in an output frame format, comprising,

an elastic store,

means for controlling writing incoming data bits into said elastic store,

means for controlling reading data bits out of said elastic store, and

means for controlling stuffing of bits into stuffing bit positions,

said means for controlling writing including means for controllably increasing the duration of a first predetermined number of intervals during which data bits are written into said elastic store and for controllably decreasing the duration of a second predetermined number of intervals during which data bits are written into said elastic store, wherein a fractional stuffing ratio is obtained.

15. A synchronizer as defined in claim 14 wherein said means for controlling stuffing includes means for controllably inserting a data bit in a stuffing bit position occurring during each of said first predetermined number of intervals and for inserting a non-data bit in a stuffing bit position occurring during each of said second predetermined number of intervals.

16. A synchronizer as defined in claim 15 wherein said means for controlling reading includes means for generating read addresses of memory locations in said elastic store out of which data bits are being read and read storing means for controllably storing the one of said read addresses being generated at a prescribed time during said intervals, wherein said means for controlling writing further includes means for generating write addresses of memory locations in said elastic store into which data bits are being written and means for controllably storing a write address, and wherein said write storing means for controlling increasing and decreasing includes means for controlling said write storing means to store a write address at prescribed instants relative to the storing of said read address so that said increasing and decreasing is effected.

17. A synchronizer as defined in claim 16 wherein said data bits are read out of said elastic store in predetermined output frame intervals and said one of the read addresses is stored in said read storing means at a fixed time during each of said output frame intervals and said first predetermined number and said second predetermined number form a multi-frame having a total number of output frames equal to the sum of said first and second predetermined numbers.

18. The synchronizer as defined in claim 17 wherein said fractional stuffing ratio is obtained for said multi-frame and is equal to said first predetermined number divided by said predetermined total number.

19. A method of synchronizing digital signals at a first transmission bit rate by use of bit stuffing to a second higher transmission bit rate for transmission in an output frame format, comprising the steps of,

increasing the duration of a first predetermined number of intervals during which incoming data bits are written into a bit stuffing synchronizer, and

decreasing the duration of a second predetermined number of intervals during which incoming data bits are written into said bit stuffing synchronizer, wherein a fractional stuffing ratio is obtained.

20. The method as defined in claim 19 further including the steps of inserting a data bit in a stuffing bit position occurring during each of said first predetermined number of intervals, and inserting a non-data bit in a stuffing bit position occurring during each of said second predetermined number of intervals.