One-chip data processing device including low voltage detector

• US 4,766,567 A
• Filed: 04/11/1985
• Issued: 08/23/1988
• Est. Priority Date: 04/19/1984
• Status: Expired due to Term

• Current Assignee: Nippondenso Company Limited 1-1 Showa-Cho Kariya-Shi Aichi Japan
• Original Assignee: Nippondenso Co., Ltd. (DENSO Corporation)
• Inventors: Kato, Mitsuharu
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US06/722,075
• Time in Patent Office: 1,230 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 307/409, 307/480, 307/517, 307/522, 365/228, 371/12, 371/66
• US Class Current: 714/22
• CPC Class Codes: G06F 11/0754 by exceeding limits
• CPC Class Codes: G06F 11/1441 Resetting or repowering

Abstract

A one-chip semiconductor device comprises a semi-conductor substrate with power supply terminals and data terminals. Formed on the substrate are a clock generating circuit for generating a clock signal when a power supply voltage is applied to it through the power supply terminals, a data processing circuit which is driven by the clock signal to process the data supplied to it through the data terminals, a first voltage detecting circuit for producing a stop signal when it detects that the power supply voltage falls below a first reference voltage, and a second voltage detecting circuit for producing a reset signal when it detects that the power supply voltage falls below a second reference voltage. The stop signal stops the clock generating circuit, whereby the data processing circuit stops and remains in the same condition as is driven by the clock signal. The reset signal initializes the data processing circuit. The first reference voltage is the lowest value which enables the data processing circuit to operate stably. The second reference voltage is the lowest value which enables the data processing circuit to remain in the same condition as is driven by the clock signal.

Claims

1. A one-chip semiconductor device comprising:

a semiconductor substrate;

a plurality of power supply terminals mounted on said substrate and adapted to be coupled to an external power source;

a plurality of data terminals mounted on said substrate for receiving data from and outputting data to an external device;

clock generating means formed on said substrate for generating a clock signal when supplied with a power supply voltage from the external power source;

data processing means formed on said substrate and driven by the clock signal supplied from said clock generating means, for processing the data supplied from said data terminals;

first voltage detecting means formed on said substrate for comparing the power supply voltage with a first reference voltage, said first reference voltage of a level above which said data processing means operates stably;

clock stopping means formed on said substrate, for producing a clock stop signal when the power supply voltage falls below the first reference voltage, thereby stopping said clock generating means;

interruption processing means, formed on said substrate and connected to receive said clock stop signal, for interrupting said data processing means and maintaining the condition thereof when said clock generating means is stopped;

second voltage detecting means, formed on said substrate, for comparing the power supply voltage with a second reference voltage, said second reference voltage of a level above which said data processing means can retain its contents; and

initializing means formed on said substrate, for producing an initializing signal to the data processing means when the power supply voltage falls below the second reference voltage, thereby initializing said data processing means to restart the operation from a beginning of its operation.

2. A one-chip semiconductor device according to claim 1, wherein the first reference voltage is slightly higher than the lowest voltage which enables said data processing means to operate stably, and the second reference voltage is slightly higher than the lowest voltage which enables said data processing means to remain in the same condition.

3. A one-chip semiconductor device according to claim 1, wherein said data processing means is a static circuit and remains in the same condition when stopped by said interruption processing means.

4. A one-chip semiconductor device according to claim 1, wherein said clock stopping means includes means, controlled by the clock signal, to provide a clock cycle of a minimum length required by said data processing means to execute an instruction.

5. A one-chip semiconductor device according to claim 1, wherein said clock generating means can generate a clock signal when the power supply voltage is higher than the first reference voltage.

6. A one-chip data processing device comprising:

a semiconductor substrate;

a plurality of power supply terminals mounted on said substrate and adapted to be coupled to an external power source;

a plurality of data terminals mounted on said substrate for receiving data from and outputting data to an external device;

clock generating means, formed on said substrate, for generating a first clock signal, and a second clock signal of a frequency lower than that of the first clock signal, when supplied with the power supply voltage from the external power source;

clock selecting means, formed on said substrate and connected to said clock generating means, for selecting one of the clock signals generated by said clock generating means based on a signal applied thereto;

data processing means, formed on said substrate and driven by the clock signal selected by said clock selecting means, for processing said data from said data terminals;

first voltage detecting means formed on said substrate for comparing the power supply voltage with a first reference voltage, said first reference voltage being a level above which said data processing circuit can operate stably;

selecting signal generating means, formed on said substrate and responsive to said first voltage detecting means, for producing a signal to command said clock selecting means to select the first clock signal when said power supply voltage is above the first reference voltage, and for producing a signal to command said clock selecting means to select the second clock signal when said power supply voltage is below the first reference voltage;

a second voltage detecting means, formed on said substrate, for comparing the power supply voltage with a second reference voltage, said second reference voltage being a level above which said data processing circuit can operate when the second clock signal is supplied to the data processing; and

initializing means formed on said substrate for producing an initializing signal to the data processing means when the power supply voltage falls below the second reference voltage, thereby initializing said data processing means to restart the operation from a beginning of its operation.

7. A one-chip semiconductor device according to claim 6, wherein the first reference voltage is slightly higher than the lowest voltage which enables said data processing means to operate stably, and the second reference voltage is slightly higher than the lowest voltage which enables said data processing means to operate when the second clock signal is supplied to the data processing means.

8. A one-chip semiconductor device according to claim 6, wherein said clock selecting means operates in synchronism with the selected clock signal to select the other clock signal.

14. A one-chip data processing device according to claim 6, wherein said data processing circuit is a dynamic circuit including a dynamic RAM.

15. A one-chip data processing device according to claim 6, wherein said clock generating circuit includes frequency control means for lowering the frequency of the second clock signal in accordance with a decrease in the power supply voltage.

16. A one-chip data processing device according to claim 15, wherein said frequency control means includes a ring oscillator.

9. A one-chip data processing device comprising:

a semiconductor substrate;

a plurality of power supply terminals mounted on said substrate and adapted to be coupled to an external power source;

a plurality of data terminals mounted on said substrate for receiving data from and outputting data to an external device;

clock generating means, formed on said substrate, for generating a first clock signal, and a second clock signal of a frequency lower than that of the first clock signal, when supplied with the power supply voltage from the external power source;

clock selecting means, formed on said substrate and connected to said clock generating means, for selecting one of the clock signals generated by said clock generating means based on a signal applied thereto;

data processing means, formed on said substrate and driven by the clock signal selected by said clock selecting means, for processing said data from said data terminals;

program counter means formed on said substrate for maintaining a program count to said data processing means to process data;

instruction decoder means formed on said substrate for outputting a non-operation instruction;

first voltage detecting means, formed on said substrate, for comparing the power supply voltage with a first reference voltage, said first reference voltage being a level above which said data processing means can operate stably;

select signal generating means, formed on said substrate and responsive to said first voltage detecting means, for producing a signal to command said clock selecting means to select the first clock signal when said power supply voltage rises above the first reference voltage, and for producing a signal to command said clock selecting means to select the second clock signal when said power supply voltage falls below the first reference voltage;

actuating means, formed on said substrate, for stopping said program counter means and causing said instruction decoder means to output a non-operation instruction when said first voltage detecting means detects that the power supply voltage falls below the first reference voltage;

second voltage detecting means, formed on said substrate, for comparing the power supply voltage with a second reference voltage, said second reference voltage being a level above which said data processing means can retain its contents when driven by the second clock signal; and

initializing means formed on said substrate for producing an initializing signal to the data processing means when the power supply voltage falls below the second reference voltage, thereby initializing said data processing means into a start condition to restart the operation from a beginning of its operation.

10. A one-chip semiconductor device according to claim 9, wherein the first reference voltage is slightly higher than the lowest voltage which enables said data processing means to operate stably, and the second reference voltage is slightly higher than the lowest voltage which enables said data processing means to remain in the same condition when the second clock signal is supplied to the data processing means.

11. A one-chip semiconductor device according to claim 9, wherein said actuating means is synchronized with one of the first clock signal or the second clock signal.

17. A one-chip data processing device according to claim 9, wherein said data processing circuit is a dynamic circuit including a dynamic RAM.

12. A one-chip data processing device comprising:

a semiconductor substrate;

a plurality of power supply terminals mounted on said substrate and adapted to be coupled to an external power source;

a plurality of data terminals mounted on said substrate, for receiving data input from, and outputting data to, an external device;

clock generating means, formed on said substrate, for generating a clock signal which has a frequency determined by a control signal;

data processing means, formed on said substrate and connected to said clock generating means and said data terminals, and driven by the clock signal generated by said clock generating means, for processing said data input from said data terminals;

voltage detecting means, formed on said substrate and connected to the power supply terminals, for detecting a power supply voltage level;

clock frequency control means, formed on said substrate and connected to said clock generating means and said voltage detecting means, for producing said control signal used for controlling said clock generating means such that a frequency of the clock signal is lowered when a decrease in said power supply voltage level is detected by said voltage detecting means; and

initializing means, formed on said substrate, for producing an initializing signal to said data processing means when the power supply voltage level detected by said voltage detecting means, falls below a range that ensures a normal state of said data processing means, to restart the operation of said data processing means from a beginning of its operation.

13. A one-chip data processing device according to claim 12, wherein said data processing means is a dynamic circuit including a dynamic RAM.