Programmable logic array

• US 4,766,569 A
• Filed: 06/05/1986
• Issued: 08/23/1988
• Est. Priority Date: 03/04/1985
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Josephson, Gregg R., Turner, John E.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US06/871,063
• Time in Patent Office: 810 Days
• Field of Search: 365/104, 365/185, 365/189, 365/201, 364/715, 364/716, 307/465, 340/825.83, 371/21, 371/25
• US Class Current: 365/185.11
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: H03K 19/17712 one of the matrices at least being reprogrammable

Abstract

A programmable logic array is disclosed employing arrays of electrically erasable and programmable cells. The device includes a dual purpose programming circuit which is employed to provide programming data to the AND array to program the AND array cells, and to provide OR array row selection data during OR array programming, thereby eliminating the need for a separate OR array row decoder. A method and apparatus is also disclosed for efficiently testing the AND array cells and input circuitry by bulk stripe programming the array cells.

Claims

1. A programmable logic array comprising:

a first array having a plurality of first cells arranged in rows and columns for providing first logical outputs respectively associated with the columns of said first cells, said logical outputs including first logical combinations of logical inputs respectively available at said first cells of respective rows, said first logical combinations being of selectively programmed ones of said first cells in respective columns;

a second array having a plurality of second cells arranged in rows and columns for providing second logical combinations of said first array logical outputs respectively available at said second cells of respective rows, said second logical combinations being of selectively programmed ones of said second cells in respective columns;

storage means for selectively storing either (a) first array row address information and first array row programming information, or (b) second array row address information and second array row programming information;

row addressing means responsive to said first array row address information and associated with said first array for selectively enabling a selected row of said first array for programming pursuant to said first array row programming information stored in said storage means;

switching means respectively associated with said columns of cells of said first array for controlling said first logical outputs to alternatively provide said second array row address information as said first array logical outputs; and

means responsive to said second array row address information contained in said first array logical outputs for enabling the programming of a selected row of said second array pursuant to said second array programming information stored in said storage means.

2. The programmable logic array of claim 1 wherein each of said first array cells includes an MOS select transistor and an MOS floating gate transistor, wherein said select transistor receives one of said logical inputs and wherein said floating gate transistor is selectively programmed to be conductive or non-conductive.

3. The programmable logic array of claim 1 wherein each of said second array cells includes an MOS select transistor and an MOS floating gate transistor, wherein said select transistor receives one of said first array logical outputs and wherein said floating gate transistor is selectively programmed to be conductive or non-conductive.

4. The programmable logic array of claim 1 wherein said storage means comprises a serial shift register having a first section of respective stages for the columns of cells of said first array, said respective stages selectively storing either (a) said first array row programming information or (b) said second array row address information.

5. The programmable logic array of claim 4 wherein said storage means further includes a second section of respective stages for the columns of cells of said second array for storing said second array row programming information.

6. The programmable logic array of claim 5 wherein said switching means includes respective switched transistors for selectively causing the contents of said first section of respective stages of said serial shift register to control the logical states of said first array logical outputs.

7. The programmable logic array of claim 1 wherein said row addressing means comprises row address decoding circuitry respectively associated with the rows of cells of said first array.

8. A method for programming the cells of a programmable logic array having (a) a first array of cells arranged in rows and columns for providing first logical outputs respectively associated with the columns of first cells, where the first logical outputs include first logical combinations of logical inputs respectively available at the cells of respective rows, and (b) a second array of cells arranged in rows and columns for providing second logical outputs respectively associated with the columns of second cells, where the second logical outputs include logical combinations of the first logical outputs respectively available at the second cells of respective rows, comprising the steps of:

(a) serially shifting into a shift register first array row selection information and program information for a selected row of cells of the first array to be programmed;

(b) enabling the selected row of cells of the first array to store the program information contained in the shift register;

(c) repeating the foregoing steps (a) through (b) as required to achieve the desired programming of the first array of cells;

(d) serially shifting into the shift register second array row selection information and program information for a selected row of the second array to be programmed;

(e) enabling each of the logical outputs of the first array to respectively provide the row selection information to the second array of cells;

(f) enabling the selected row of cells in the second array to store the program information contained in the shift register; and

(g) repeating the foregoing steps (d) through (f) to achieve the desired programming of the second array of cells.

9. A method for functional testing of a programmable logic device having an array of electrically erasable and reprogrammable cells arranged in rows and columns, the programmable logic device providing logical outputs which include logical combinations of logical inputs provided to the electrically erasable array, comprising the steps of:

(a) erasing the array cells so that none of the cells contribute to the logical outputs when interrogated;

(b) programming in a single programming cycle the cells in a first set of alternating rows to contribute to the logical outputs when interrogated;

(c) driving the device inputs with device input signals so that the logical inputs to the first set of rows are at a logical level which does not interrogate the cells of said rows and the logical inputs to the second set of rows are at the cell interrogation logical level;

(d) comparing the logical outputs with an expected output signal pattern;

(e) sequentially toggling the state of each device input signal and comparing the logical outputs with expected output signal patterns to verify the operation of the contributing cells and associated input circuitry;

(f) erasing the array cells so that none of the cells in the first or second sets of rows contribute to the logical outputs when interrogated;

(g) programming in a single programming cycle the cells in said second set of rows to contribute to the logical outputs when interrogated;

(h) driving the device inputs with device input signals so that the logical inputs to the first set of rows are at the cell interrogation logical level, and the logical inputs to the second set of rows are at a logical level which does not interrogate the row cells; and

(i) repeating steps (d) and (e).

10. The method of claim 9 wherein said step (a) comprises the step of erasing all cells of the array to a first state wherein the cells do not contribute to the logical outputs when interrogated, and wherein said step (b) comprises the steps of:

(i) selecting the cells in the first set of rows to be programmed to a second state wherein the cells contribute to the logical outputs when interrogated; and

(ii) in a single programming cycle, programming said selected cells to the second state.

11. The method of claim 9 wherein said step (f) comprises the step of erasing all cells of the array to a first state wherein the cells do not contribute to the logical outputs when interrogated, and wherein said step (g) comprises the steps of:

(i) selecting the cells in said second set of rows to be programmed to a second state wherein the cells contribute to the logical outputs when interrogated; and

(ii) in a single programming cycle, programming the selected cells to said second state.

12. A programmable logic device for providing logical outputs which include logical combinations of device input signals, comprising:

a plurality of device lines for receiving the device input signals;

an input circuit coupled to the device input lines for providing logical array input signals which are true and complement versions of the device input signals;

an array of electrically erasable and reprogrammable cells arranged in rows and columns, each row of cells being coupled to a particular one of said logical array input signals, said array providing logical combinations of the array input signals;

means responsive to said array for providing logical outputs which include said logical combinations of the array input signals;

means for selectively programming said cells to achieve a desired device logic configuration; and

testing means for testing the operation of the programmable logic device, comprising means for bulk stripe programming in a single programming cycle all cells in rows associated with either the true or complement versions of the device input signals to a first state wherein the cells contribute to the logical outputs when interrogated.

13. The device of claim 12 wherein said programming means comprises:

select means associated with each cell for selecting said cell to be erased or programmed during a particular programming cycle;

row addressing means responsive to a row address word comprising a least significant bit and at least one other more significant bit, said word defining a particular one of the array rows to said first state and selecting the cells in said defined row; and

programming circuitry arranged to program particular ones of the cells in said defined row to said first state in dependence on programming data defining which cells in the defined row are to be programmed.

14. The device of claim 13 wherein said testing means comprises means coupled to said row addressing means and responsive to a bulk stripe signal for causing said row addressing means to select all cells in either all rows associated with true version or all rows associated with said complement versions, in dependence on the state of said least significant bit of said row address word.

15. The device of claim 14 wherein the even rows of said array are associated with respective ones of either said true or complement versions, and the odd rows of said array are associated with respective ones of the other of said true or complement versions, and wherein said means responsive to said bulk stripe signal causes either the odd array rows or the even array rows to be selected for programming in dependence on the state of said least significant bit.