Double layer photoresist process for well self-align and ion implantation masking
First Claim
1. A process for forming closely aligned wells or tubs in a semiconductor substrate comprising:
- (a) providing a semiconductor substrate and depositing a resist mask thereon comprising a lower layer of a first photoresist material and an upper layer of a second photoresist layer, with an opening defining the lateral extent of a first well, said resist mask defining an overhang structure around the periphery of said opening, the thickness of said resist mask being sufficient to withstand ion bombardment;
(b) implanting ions through said opening to form a first well;
(c) depositing discontinuous metal over said resist mask and opening to thereby cover said first well, the thickness of said metal covering said first well being sufficient to withstand ion bombardment;
(d) removing said resist mask and metal thereon, leaving in place the metal covering said first well; and
(e) implanting ions into said substrate adjacent the metal covering said first well to thereby form a second well directly adjacent said first well, whereby adjacent twin wells are formed in a relatively high yield process requiring a relatively low number of individual process steps.
1 Assignment
0 Petitions
Accused Products
Abstract
A technique is disclosed for obtaining a self-aligned twin-well structure in a CMOS process. A double layer of two different photoresist materials is employed to obtain an overhang photoresist structure used for the p-well masking and ion implantation process. After the p-well implantation, pure aluminum is deposited over the wafer, forming a first layer over the p-well region and a second layer over the photoresist layers. A metal lift-off procedure is performed to dissolve the photoresist layers and thereby remove the second layer of metal. The first layer of aluminum remaining on the wafer forms a conjugate of the p-well pattern and serves as the n-well mask for ion implantation. The invention provides a straightforward method for achieving the self-aligned twin-well structure in CMOS processes, and is adapted to high energy ion implantation for achieving retrograde impurity profiles.
-
Citations
25 Claims
-
1. A process for forming closely aligned wells or tubs in a semiconductor substrate comprising:
-
(a) providing a semiconductor substrate and depositing a resist mask thereon comprising a lower layer of a first photoresist material and an upper layer of a second photoresist layer, with an opening defining the lateral extent of a first well, said resist mask defining an overhang structure around the periphery of said opening, the thickness of said resist mask being sufficient to withstand ion bombardment; (b) implanting ions through said opening to form a first well; (c) depositing discontinuous metal over said resist mask and opening to thereby cover said first well, the thickness of said metal covering said first well being sufficient to withstand ion bombardment; (d) removing said resist mask and metal thereon, leaving in place the metal covering said first well; and (e) implanting ions into said substrate adjacent the metal covering said first well to thereby form a second well directly adjacent said first well, whereby adjacent twin wells are formed in a relatively high yield process requiring a relatively low number of individual process steps. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. In a process for producing twin wells implanted with doping materials in the manufacture of complimentary MOS (CMOS) field effect transistor circuits, the improvement comprising a sequence of the following steps:
-
(i) applying a first layer of a first photoresist material to a semiconductor wafer; (ii) applying a second layer of a second photoresist material to said first layer to form a double layer of photoresist on the wafer; (iii) employing a first well mask to selectively expose the second layer of photoresist material, and thereafter developing the second layer in the first well pattern to provide a first well opening in the second photoresist material; (iv) selectively exposing and thereafter developing the first layer of photoresist through the first well pattern opening formed in the second layer of photoresist; (v) using the photoresist structure to selectively screen the wafer, providing impurities of a first conductivity type into unscreened portions of the wafer to form a first well region; (vi) depositing metal onto the patterned wafer, whereby a first metal layer is deposited over the first well region and a second metal layer is formed over the first and second photoresist layer, wherein a gap is formed between the first and second metal layers; (vii) removing the first and second layer of photoresist to lift off the second layer of metal from the wafer; and (viii) using the first layer of metal to selectively screen the wafer, providing impurities of a second conductivity type into the unscreened portions of the wafer to form a second well region. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
-
-
18. A complimentary metal-oxide-semiconductor (CMOS) process, comprising the steps of:
-
(i) forming a relatively thick layer of a first photoresist material on a silicon substrate; (ii) forming a relatively thin layer of a second photoresist material on said layer of said first photoresist material, said first and second photoresist materials being selected so that one is exposed and developed by dissimilar process steps from those required to expose and develop the other; (iii) employing a first well mask to selectively expose the layer of the second photoresist material, and thereafter developing said material to provide a first well opening pattern in the second photoresist material; (iv) exposing and developing the first photoresist material through the first well pattern formed in the second photoresist material so as to form an overhang structure, wherein the second photoresist material overhangs the first photoresist material about the well opening; (v) using the photoresist overhang structure to selectively screen the wafer, providing impurities of a first conductivity type into unscreened portions of the substrate to form a first well region of said first conductivity type; (vi) depositing metal onto the patterned layer, whereby a first metal layer is deposited over the first well region of the substrate, and a conjugate second layer is formed on the second photoresist material, the second metal layer being elevated by the photoresist materials in relation to the first metal layer; (vii) removing the first and second photoresist materials to lift the second metal layer off the substrate; and (viii) using the first layer of metal to selectively screen the substrate, providing impurities of a second conductivity type into the unscreened portions of the substrate to form a second well region of a second conductivity type in a self-aligned relationship with the first well region. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25)
-
Specification