Double layer photoresist process for well self-align and ion implantation masking

• US 4,767,721 A
• Filed: 02/10/1986
• Issued: 08/30/1988
• Est. Priority Date: 02/10/1986
• Status: Expired due to Fees

• Current Assignee: Hughes Aircraft Company (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Lee, William W. Y., Liao, Kuan Y.
• Primary Examiner(s): Roy, Upendra
• Application Number:
  US06/827,140
• Time in Patent Office: 932 Days
• Field of Search: 437/29, 437/34, 437/56, 437/944, 357/42
• US Class Current: 438/420
• CPC Class Codes: H01L 21/0272 for lift-off processes
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: Y10S 438/951 Lift-off

Abstract

A technique is disclosed for obtaining a self-aligned twin-well structure in a CMOS process. A double layer of two different photoresist materials is employed to obtain an overhang photoresist structure used for the p-well masking and ion implantation process. After the p-well implantation, pure aluminum is deposited over the wafer, forming a first layer over the p-well region and a second layer over the photoresist layers. A metal lift-off procedure is performed to dissolve the photoresist layers and thereby remove the second layer of metal. The first layer of aluminum remaining on the wafer forms a conjugate of the p-well pattern and serves as the n-well mask for ion implantation. The invention provides a straightforward method for achieving the self-aligned twin-well structure in CMOS processes, and is adapted to high energy ion implantation for achieving retrograde impurity profiles.

Claims

1. A process for forming closely aligned wells or tubs in a semiconductor substrate comprising:

(a) providing a semiconductor substrate and depositing a resist mask thereon comprising a lower layer of a first photoresist material and an upper layer of a second photoresist layer, with an opening defining the lateral extent of a first well, said resist mask defining an overhang structure around the periphery of said opening, the thickness of said resist mask being sufficient to withstand ion bombardment;

(b) implanting ions through said opening to form a first well;

(c) depositing discontinuous metal over said resist mask and opening to thereby cover said first well, the thickness of said metal covering said first well being sufficient to withstand ion bombardment;

(d) removing said resist mask and metal thereon, leaving in place the metal covering said first well; and

(e) implanting ions into said substrate adjacent the metal covering said first well to thereby form a second well directly adjacent said first well, whereby adjacent twin wells are formed in a relatively high yield process requiring a relatively low number of individual process steps.

2. The process of claim 1 wherein said opening is formed in said upper resist layer, and said first resist material is subsequently exposed and overdeveloped so as to form said overhang structure.

3. The invention of claim 1 wherein said step of removing said resist mask and metal thereon comprises:

(i) immersing said substrate in a resist dissolving solution; and

(ii) vibrating the immersed substrate by ultrasonic vibration means, whereby the resist is removed and the metal thereon lifted off the substrate.

4. The process of claim 1 wherein said step of implanting ions to form a first well comprises high energy, high dose implantation and wherein said resist layer is adapted to sustain said high energy, high dose implantation.

5. The process of claim 2 wherein said step of depositing discontinuous metal over said resist mask comprises metal deposition at a deposition angle of about 90°

, and said resist mask defines an overhang structure around the periphery of said opening, whereby the metal covering the resist mask is discontinuous with the metal covering of said first well.

6. The process of claim 5 wherein said step of depositing discontinuous metal over said resist mask comprises the steps of:

providing an electron beam evaporation source for evaporating a metal charge;

providing an evaporation chamber about said source, said chamber being defined by a chamber surface comprising a hemispherical surface;

whose radius is cooperatively selected with the shape of said charge so that the metal is evaporated toward said hemispherical surface at about a 90°

deposition angle;

affixing said substrate inside said chamber adjacent said hemispherical surface; and

operating said source to evaporate said metal charge.

7. In a process for producing twin wells implanted with doping materials in the manufacture of complimentary MOS (CMOS) field effect transistor circuits, the improvement comprising a sequence of the following steps:

(i) applying a first layer of a first photoresist material to a semiconductor wafer;

(ii) applying a second layer of a second photoresist material to said first layer to form a double layer of photoresist on the wafer;

(iii) employing a first well mask to selectively expose the second layer of photoresist material, and thereafter developing the second layer in the first well pattern to provide a first well opening in the second photoresist material;

(iv) selectively exposing and thereafter developing the first layer of photoresist through the first well pattern opening formed in the second layer of photoresist;

(v) using the photoresist structure to selectively screen the wafer, providing impurities of a first conductivity type into unscreened portions of the wafer to form a first well region;

(vi) depositing metal onto the patterned wafer, whereby a first metal layer is deposited over the first well region and a second metal layer is formed over the first and second photoresist layer, wherein a gap is formed between the first and second metal layers;

(vii) removing the first and second layer of photoresist to lift off the second layer of metal from the wafer; and

(viii) using the first layer of metal to selectively screen the wafer, providing impurities of a second conductivity type into the unscreened portions of the wafer to form a second well region.

8. The invention of claim 7 wherein said step of providing said impurities of said second conductivity type comprises ion implantation.

9. The invention of claim 7 wherein said step of providing said impurities of said second conductivity type comprises ion implantation.

10. The invention of claim 7 wherein said step of depositing metal onto the patterned wafer comprises vacuum deposition of said metal.

11. The invention of claim 7 wherein said step of removing the first and second layers of photoresist material to lift off the second layer of metal comprises:

(i) immersing the wafer in a solution which dissolves the photoresist materials for a period of time; and

(ii) vibrating the immersed wafer by ultrasonic vibration means, whereby the photoresist layers are removed and said second layer of metal is lifted off the wafer.

12. The invention of claim 7 wherein said first layer of metal is formed in the conjugate of the first well mask.

13. The invention of claim 7 wherein said step of exposing and developing the first layer of photoresist form an overhang photoresist structure, wherein the second layer of photoresist defining the first well opening overhangs the portion of the first layer defining the first well opening.

14. The invention of claim 7 wherein said first and second photoresist materials have good adhesion to each other, and are exposed and developed by dissimilar process steps.

15. The invention of claim 7 wherein said step of applying said first layer of said first photoresist material comprises:

(a) applying a first coating of said first photoresist material;

(b) hard baking the coated wafer;

(c) applying a second coating of said first photoresist material; and

(d) hard baking the coated wafer;

whereby a relatively thick layer of the first photoresist layer is formed on the wafer.

16. The invention of claim 11 wherein during said step of vibrating the immersed wafer, the wafer is suspended in the developing solution.

17. The invention of claim 15 wherein said step of applying said second layer of said second photoresist material results in a relatively thin layer.

18. A complimentary metal-oxide-semiconductor (CMOS) process, comprising the steps of:

(i) forming a relatively thick layer of a first photoresist material on a silicon substrate;

(ii) forming a relatively thin layer of a second photoresist material on said layer of said first photoresist material, said first and second photoresist materials being selected so that one is exposed and developed by dissimilar process steps from those required to expose and develop the other;

(iii) employing a first well mask to selectively expose the layer of the second photoresist material, and thereafter developing said material to provide a first well opening pattern in the second photoresist material;

(iv) exposing and developing the first photoresist material through the first well pattern formed in the second photoresist material so as to form an overhang structure, wherein the second photoresist material overhangs the first photoresist material about the well opening;

(v) using the photoresist overhang structure to selectively screen the wafer, providing impurities of a first conductivity type into unscreened portions of the substrate to form a first well region of said first conductivity type;

(vi) depositing metal onto the patterned layer, whereby a first metal layer is deposited over the first well region of the substrate, and a conjugate second layer is formed on the second photoresist material, the second metal layer being elevated by the photoresist materials in relation to the first metal layer;

(vii) removing the first and second photoresist materials to lift the second metal layer off the substrate; and

(viii) using the first layer of metal to selectively screen the substrate, providing impurities of a second conductivity type into the unscreened portions of the substrate to form a second well region of a second conductivity type in a self-aligned relationship with the first well region.

19. The invention of claim 18 wherein said step of exposing and developing the first photoresist material is adapted to allow selection of a desired width of said overhang structure.

20. The invention of claim 18 wherein said first well is a p-type well, and said second well is an n-type well.

21. The invention of claim 18 wherein said step of providing impurities of a first conductivity type comprises ion implantation of said impurities.

22. The invention of claim 18 wherein said step of providing impurities of a second conductivity type comprises ion implantation of said impurities.

23. The invention of claim 18 further including the step of hard baking the substrate and said layers of photoresist materials before the step of providing impurities of said impurities of said first conductivity type into said substrate.

24. The invention of claim 18 wherein said step of removing the first and second photoresist materials to lift off the second metal layer comprises:

(a) immersing the substrate in a solution which dissolves the photoresist materials; and

(b) vibrating the immersed substrate, whereby the second metal layer is lifted off the substrate.

25. The invention of claim 24 wherein said substrate is vibrated by ultrasonic vibration means, and wherein said substrate is suspended in said solution while said vibration occurs.