Recrystallized CMOS with different crystal planes

• US 4,768,076 A
• Filed: 09/11/1985
• Issued: 08/30/1988
• Est. Priority Date: 09/14/1984
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Isomae, Seiichi, Sakai, Yoshio, Ikeda, Shuji, Aoki, Masaaki, Warabisako, Terunori, Meguro, Satoshi, Masuhara, Toshiaki, Hanamura, Shoji
• Primary Examiner(s): Larkins, William D.
• Application Number:
  US06/774,705
• Time in Patent Office: 1,084 Days
• Field of Search: 357/60, 357/23.7, 357/42
• US Class Current: 257/70
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes

Abstract

A CMOS IC is formed on a semiconductor crystalline surface having a plane azimuth (110) or (023), or of a plane azimuth close thereto (plane azimuth substantially in parallel with the above-mentioned planes), in order to increase the speed of operation.

At low temperatures, dependency of the carrier mobility upon the plane azimuth becomes more conspicuous as shown in FIG. 1, and the difference of mobility is amplified depending upon the planes. Therefore, employment of the above-mentioned crystalline planes helps produce a great effect when the CMOS device is to be operated at low temperature (e.g., 100° K. or lower), and helps operate the device at high speeds.

Claims

1. A semiconductor device comprising:

a semiconductor substrate which has a first substantially flat surface lying substantially parallel to a (100) plane;

an insulating film formed on said first substantially flat surface;

a semiconductor layer, which is deposited on said insulating film and recrystallized by laser irradiation, and which has a second substantially flat surface lying substantially parallel to a (110) plane; and

source and drain regions of a n-channel MOS transistor formed at said first substantially flat surface of said semiconductor substrate, and source and drain regions of a p-channel MOS transistor formed at said second substantially flat surface of said semiconductor layer.

2. A semiconductor device according to claim 1, wherein said semiconductor substrate and said semiconductor layer are formed of silicon.

3. A semiconductor device according to claim 2, wherein said semiconductor substrate has p-type conductivity.

4. A semiconductor device according to claim 1, wherein said insulating film includes at least a Si₃ N₄ film.

5. A semiconductor device according to claim 1, wherein said p-channel MOS transistor and said n-channel MOS transistor are connected with each other so as to form an inverter.

6. A semiconductor device according to any one of claims 1-5, wherein said semiconductor device is adapted to operate at a temperature below 100°

K.

7. A semiconductor device comprising:

a semiconductor substrate which has a first substantially flat surface lying substantially parallel to a (100) plane;

an insulating film formed on said substantially flat surface;

a semiconductor layer, which is deposited on said insulating film and recrystallized, and which has a second substantially flat surface lying substantially parallel to a (110) plane; and

source and drain regions of a n-channel MOS transistor formed at said first substantially flat surface of said semiconductor substrate, and source and drain regions of a p-channel MOS transistor formed at said second substantially flat surface of said semiconductor layer.

8. A semiconductor device according to claim 7, wherein said semiconductor substrate and said semiconductor layer are formed of silicon.

9. A semiconductor device according to claim 8, wherein said semiconductor substrate has p-type conductivity.

10. A semiconductor device according to claim 8, wherein said insulating film includes at least Si₃ N₄ film.

11. A semiconductor device according to claim 8, wherein said p-channel MOS transistor and said n-channel MOS transistor are connected with each other so as to form an inverter.

12. A semiconductor device according to any one of claims 7-11, wherein said semiconductor device is adapted to operate at temperature below 100°

K.