System for managing a plurality of shared interrupt handlers in a linked-list data structure

• US 4,768,149 A
• Filed: 08/29/1985
• Issued: 08/30/1988
• Est. Priority Date: 08/29/1985
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Konopik, Bradly J., Reed, Martin A., Tannenbaum, Alan R., Bradley, David J., Turner, Michael R.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/770,541
• Time in Patent Office: 1,097 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/300
• US Class Current: 710/47
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

A system is disclosed for managing a plurality of interrupt handlers in a linked-list data structure, for servicing a plurality of input/output devices sharing a common interrupt line in a microcomputer. The system provides for an orderly method to link a newly loaded interrupt handler routine into a linked-list data structure consisting of previously loaded interrupt handler routines. The system further provides for an orderly method to share a common interrupt line among a plurality of input/output devices being serviced by the interrupt handlers. The system further provides for an orderly means to unlink a particular interrupt handler routine from the linked-list data structure when a corresponding input/output device is to be deactivated. The system finds special utility in a multitasking operating system environment where input/output devices can be deactivated in a different sequence from that in which they were originally activated.

Claims

1. In a microcomputer including a central computing means, a memory and a plurality of I/O devices connected together by a bus, each of said I/O devices having an output connected to a common interrupt line, for transmitting a corresponding interrupt signal on said interrupt line, and each of said I/O devices having an input connected to said common interrupt line, for monitoring said interrupt line for an occurrence of an interrupt signal thereon and for blocking a transmission of subsequently occurring interrupt signals in response thereto, a system for enabling said I/O devices to share said common interrupt line, comprising:

a plurality of interrupt handler rountines stored as an ordered chain in said memory, each having an instruction portion containing an ordered sequence of instructions executable by said central computing means, to service interrupt demands of a respective one of said I/O device, and each interrupt handler routine having a control block portion located at a fixed relative position from a beginning instruction position of said instruction portion, for storing a pointer address to a beginning instruction position of the instruction portion for a next occuring interrupt handler routine in said chain;

said central computing means interrupting an existing execution of a main program and accessing over said bus, an interrupt vector location in said memory in response to an interrupt signal on said interrupt line, said vector location storing the address of a beginning instruction position of the instruction portion for a first occurring interrupt handler routine in said chain corresponding to a first I/O device of said plurality of I/O devices;

said central computing means executing a status determination segment of said instruction portion of said first interrupt handler routine and in response thereto, accessing over said bus, an interrupt status value stored by said first I/O device, and determining whether said first I/O device caused said interrupt signal to be transmitted on said interrupt line;

said central computing means executing a service routine segment of said instruction portion of said first interrupt handler routine in response to a determination by said central computing means that said first I/O device caused said interrupt signal, for servicing an interrupt demand of said first I/O device;

said central computing means executing a global rearm segment of said instruction portion of said first interrupt handler routine and in response thereto, transmitting a global rearm message over said bus to all of said plurality of I/O devices, for unblocking a transmission of said subsequently occurring interrupt signals from said I/O devices, prior to returning control back to said main program;

said central computing means excuting a control transfer segment of said instruction portion of said first interrupt handler rountine in response to a determination by said central computing means that said first I/O device did not cause said interrupt signal, said central computing means in response thereto, accessing over said bus, said pointer address in said control block portion of said first interrupt handler routine, for commencing execution of the instruction portion of said next occurring interrupt handler in said chain to service interrupt demands in a corresponding second one of said I/O devices;

whereby a plurality of I/O devices can share said common interrupt line.

2. The system of claim 1, which further comprises:

said control block portion of each of said interrupt handler routines including a flag field, for indicating if a corresponding interrupt handler routine is a last occurring one in said chain;

said central computing means executing a flag evaluation segment of said instruction portion of said interrupt handler rountines, following said determination that a corresponding I/O device did not cause the interrupt signal, to evaluate if said corresponding interrupt handler routine is said last occurring one in the chain, and if it is said last occurring one in said chain, said central computing means executing said global rearm segment prior to returning control back to said main program.

3. The system of claim 1, which further comprises:

a linking routine stored in said memory, having an instruction portion containing instructions executable by said central computing means, to link a new interrupt handler routine into said chain, by storing an existing contents of said interrupt vector location in a control block portion of said new interrupt handler as a pointer address to a beginning instruction position of the instruction portion for a next occurring interrupt handler rountine in the chain, and storing the address to a beginning instruction position of the instruction portion of said new routine in said interrupt vector location in said memory.

4. The system of claim 1, which further comprises:

an unlinking routine stored in said memory, having an instruction portion containing instructions executable by said central computing means, to unlink a target interrupt handler routine by reading a contents of said interrupt vector to locate a first occurring interrupt handler in said chain, comparing an indentity of said first interrupt handler with that of said target interrupt handler, reading the pointer address in the control block portion located at a fixed relative position from a beginning instruction position of said instruction portion of said first interrupt handler to locate a next occurring interrupt handler in said chain, comparing an identity of said next interrupt handler and determining that is is said target interrupt handler, transferring the pointer in the control block portion located at a fixed relative position from a beginning instruction position of said instruction portion of said next occurring interrupt handler, into said control block poriton of said first interrupt handler;

whereby said chain of interrupt handlers will skip around said target interrupt handler.

5. In a microcomputer including a central computer means, a memory and a plurality of I/O devices connected together by a bus, a combination for enabling said plurality of I/O devices to share a common interrupt line connected to said central computing means, comprising:

a plurality of interrupt logic means, each having a first input connected to an interrupt output of a corresponding one of said plurality of I/O devices, and each having an output connected to said common interrupt line, for transmitting a corresponding interrupt signal on said common interrupt line in response to an interrupt demand output from said corresponding I/O device and storing an interrupt status value;

said interupt logic means each having a second input connected to said common interrupt line, for monitoring said common interrupt line for an occurrence of an interrupt signal thereon and for blocking a transmission of subsequently occurring interrupt signals in response thereto;

a plurality of interrupt handler rountines stored as a chain in said memory, each having an instruction portion containing instructions executable by said central computing means, to service interrupt demands of a respective one of said I/O devices, and each interrupt handler routine having a control block portion located at a fixed relative position from a beginning instruction position of said isntruction portion, for storing a pointer address to said beginning of the instruction portion for a next occurring interrupt handler routine in said chain;

said central computing means interrupting an existing execution of a main program and accessing over said bus, an interrupt vector location in said memory in response to an interrupt signal on said common interrupt line, said vector location storing the address of a beginning instruction position of the instruction portion for a first occurring interrupt handler routine in said chain corresponding to a first I/O device of said plurality of I/O devices;

said central computing means executing a status determination segment of said instruction portion of said first occurring interrupt handler routine and in response thereto, accessing over said bus, an interrupt status value stored by an interrupt logic means for said first I/O device, and determining whether said first I/O device caused said interrupt signal to be transmitted on said common interrupt line;

said central computing means exeucting a service routine segment of said instruction portion of said first occurring interrupt handler routine in response to a determination by said central computing means that said first I/O device caused said interrupt signal, for servicing said interrupt demand of said first I/O device;

said central computing means executing a global rearm segment of said instruction portion of said first occurring interrupt handler routine and in response thereto, transmitting a global rearm message over said bus to said interrupt logic means for all of said plurality of I/O devices, for unblocking a transmission of subsequently occurring interrupt signals from said I/O devices, prior to returning control back to said main program;

said central computing means executing a control transfer segment of said instruction portion of said first occurring interrupt handler routine in response to a determination by said cnetral computing means that said first I/O device did not cause said interrupt signal, said central computing means in response thereto, accessing over said bus, said pointer address in said control block portion of said first occurring interrupt handler routine, for commencing execution of the instruction portion of said next occurring interrupt handler in said chain to service interrupt demands in a corresponding second one of said I/O devices;

whereby a plurality of I/O devices can share said common interrupt line.

6. The combination of claim 5, which further comprises:

said control block portion of each of said interrupt handler routines including a flag field, for indicating if a corresponding interrupt handler routine is a last occurring one in said chain;

said central computing means executing a flag evaluation segment of said instruction portion of said interrupt handler rountines, following said determination that a corresponding I/O device did not cause the interrupt signal, to evaluate if a corresponding interrupt handler routine is a last occurring one in the chain, and if it is a last occuring one in said chain, said central computing means executing a global rearm segment prior to returning control back to said main program.

7. The combination of claim 5, which further comprises:

a linking routine stored in said memory, having an instruction portion containing instructions executable by said central computing means, to link a new interrupt handler routine into said chain, by storing an existing contents of said interrupt vector location in a control block portion of said new interrupt handler as a pointer address to a beginning instruction position of the instruction portion for a next occurring interrupt handler routine in the chain, and storing the address to a beginning instruction position of the instruction portion of said new routine in said interrupt vector location in said memory.

8. The combination of claim 5, which further comprises:

an unlinking routine stored in said memory, having an instruction portion containing instructions executable by said central computing means, to unlink a target interrupt handler routine by reading a contents of said interrupt vector to locate a first occurring interrupt handler in said chain, comprising an indentity of said first interrupt handler with that of said target interrupt handler, reading the pointer address in the control block portion located at a fixed relative position from a beginning instruction position of said instruction portion of said first interrupt handler to locate a next occurring interrupt handler in said chain, comparing an identity of said next interrupt handler and determining that it is said target interrupt handler, transferring the pointer address in the control block portion located at a fixed relative position from a beginning instructions position of said instruction portion of a next occurring interrupt handler, into said control block portion of said first interrupt handler;

whereby said chain of interrupt handlers will skip around said target interrupt handler.

9. In a microcomputer including a central computing means, a memory and a plurality of I/O devices connected together by a bus, each of said I/O devices having an output connected to a common interrupt line, for transmitting a corresponding interrupt signal on said interrupt line, and each of said I/O devices having an input connected to said common interrupt line, for monitoring said interrupt line for an occurrence of an interrupt signal thereon and for blocking a transmission of subsequently occuring interrupt singals in response thereto, a method for enabling said I/O devices to share said common interrupt line, comprising:

storing a plurality of interrupt handler rountines as an ordered chain in said memory, each having an instruction portion containing an ordered sequence of instructions executable by said central computing means, to service interrupt demands of respective one of said I/O devices, and each interrupt handler routine having a control block portion located at a fixed relative position from a beginning instruction position of said instruction portion, for storing a pointer address to a beginning instruction position of the instruction portion for a next occurring interrupt handler routine in said chain;

interrupting said central computing means during an existing of a main program and accessing over said bus, an interrupt vector location in said memory in response to an interrupt signal on said interrupt line, said vector location storing the address of a beginning instruction position of the instruction portion for a first occurring interrupt handler routine in said chain corresponding to a first I/O device of said plurality of I/O devices;

executing in said central computing means, a status determination segment of said instruction portion of said first interrupt handler routine and in response thereto, accessing over said bus, an interrupt status value stored by said first I/O device, and determining whether said first I/O device caused said interrupt signal to be transmitted on said interrupt line;

executing in said central computering means, a service routine segment of said instruction portion of said first interrupt handler routine in response to a determination by said central computing means that said first I/O device caused said interrupt signal for servicing an interrupt demand of said first I/O device;

executing in said central computing means a global rearm segment of said instruction portion of said first interrupt handler routine and in response thereto, transmitting a global rearm message over said bus to all of said plurality of of I/O devices, for unblocking a transmission of said subsequently occurring interrupt signals from said I/O devices, prior to returning control back to said main program;

executing in said central computing means, a control transfer segment of said instruction portion of said first interrupt handler routine in response to a determination by said central computing means that said first I/O device did not cause said interrupt signal, said central computing means in response thereto, accessing over said bus, said pointer address in said control block portion of said first interrupt handler routine, for commencing execution of the instruction portion of said next occurring interrupt handler in said chain too service interrupt demands in a corresponding second one of said I/O devices;

whereby a plurality of I/O devices can share said common interrupt line.

10. The method of claim 9, which further comprises:

said control block portion of each of said interrupt handler routines including a flag field, for indicating if a corresponding interrupt handler routine is a last occurring one in said chain;

executing in said central computing means, a flag evaluation segment of said instruction portion of said interrupt handler routines, following said determination that a corresponding I/O device did not cause the interrupt signal, to evaluate if said corresponding interrupt handler routine is said last occurring one in the chain, and if it is said last occurring one in said chain, said central computing means executing said global rearm segment prior to returning control back to said main program.

11. The method of claim 9, which further comprises:

a linking routine stored in said memory, having an instruction portion containing instructions executable by said central computing means, to link a new interrupt handler routine into said chain;

said linking routine storing an existing contents of said interrupt vector location in a control block portion of said new interrupt handler as a pointer address to a beginning instruction position of the instruction portion for a next occurring interrupt handler routine in the chain;

said linking routine storing the address to a beginning instruction position of the instruction portion of said new routine in said interrupt vector location in said memory.

12. The method of claim 9, which further comprises:

an unlinking routine stored in said memory, having an instruction portion containing instructions executable by said central computing means, to unlink a target interrupt handler routine;

said unlinking routine reading a contents of said interrupt vector to a locate a first occurring interrupt handler in said chain;

said unlinking routine comparing an identity of said first interrupt handler with that of said target interrupt handler;

said unlinking routine reading the pointer address in the control block portion located at a fixed relative position from a beginning instruction position of said instruction portion of said first interrupt handler to locate a next occurring interrupt handler in said chain;

said unlinking routine comparing an identity of said next interrupt handler and determining that it is said target interrupt handler;

said unlinking routine transferring the pointer address in the control block portion located at a fixed relative position form a beginning instruction posiiton of said instruction portion of said next occurring interrupt handler, into said control block portion of said first interrupt handler;

whereby said chain of interrupt handlers will skip around said target interrupt handler.

13. In a microcomputer including a central computing means, a memory and a plurality of I/O devices connected together by a bus, each of said I/O devices including an output connected to a common interrupt line, for transmitting a corresponding interrupt signal on said interrupt line, and each of said I/O devices having an input connected to said common interrupt line, for monitoring said interrupt line for an occurrence of an interrupt signal thereon and for blocking a transmission of subsequently occurring interrupt signals in response thereto, a system for enabling said I/O devices to share said common interrupt line, comprising:

a plurality of interrupt handler routines stored as a chain in said memory, to service interrupt demands of respective ones of said I/O devices, and each storing a pointer address to a beginning of a next occurring interrupt handler routine in said chain;

said central computing means interrupting an existing execution of a main program and accessing over said bus, an interrupt vector location in said memory in response to an interrupt signal on said interrupt line, said vector location storing the address of a beginning of a first occurring interrupt handler routine in said chain corresponding to a first one of said I/O devices;

said central computing means executing a status determination routine for determining whether said first one of said I/O devices caused said interrupt signal to be transmitted on said interrupt line;

said central computing means executing a service routine for servicing an interrupt demand of said first one of said I/O devices;

said central computing means executing a rearm routine for unlocking a transmission of said subsequently occurring interrupt signals from said I/O devices, prior to returning control back to said main program;

said central computing means executing a control transfer routine for commencing an execution of a next occurring interrupt handler in said chain to service interrupt demands in a corresponding second one of said I/O devices, if said first one of said I/O devices did not cause said interrupt signal;

whereby a plurality of I/O devices can share said common interrupt line.

14. In a microcomputer including a central computing means, a memory and a plurality of I/O devices connected together by a bus, each of said I/O devices having an output connected to a common interrupt line, for transmitting a corresponding interrupt signal on said interrupt line, and each of said I/O devices having an input connected to said common interrupt line, for monitoring said interrupt line for an occurrence of an interrupt signal thereon and for blocking a transmission of subsequently occurring interrupt signals in response thereto, a method for enabling said I/O devices to share said common interrupt line, comprising:

storing a plurality of interrupt handler routines as a chain in said memory, to service interrupt demands of respective ones of said I/O devices, and each storing a pointer address to a beginning of a next occurring interrupt handler routine in said chain;

interrupting said central computing means during an existing execution of a main program and accessing over said bus, an interrupt vector location in said memory in response to an interrupt signal on said interrupt line, said vector location storing the address of a beginning of a first occurring interrupt handler routine in said chain corresponding to a first one of said I/O devices;

executing in said central computing means, a status determination routine for determining whether said first one of said I/O devices caused said interrupt signal to be transmitted on said interrupt line;

executing in said central computing means, a service routine for servicing an interrupt demand of said first one of said I/O devices;

executing in said central computing means a rearm routine for unblocking a transmission of said subsequently occurring interrupt signals from said I/O devices, prior to returning control back to said main program;

executing in said central computing means, a control transfer routine for commencing an execution of a next occurring interrupt handler in said chain to service interrupt demands in a corresponding second one of said I/O devices, if said first one of said I/O devices did not cause said interrupt signal;

whereby a plurality of I/O devices can share said common interrupt line.