Memory circuit having a plurality of cell arrays

• US 4,768,171 A
• Filed: 06/20/1985
• Issued: 08/30/1988
• Est. Priority Date: 06/20/1984
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Tada, Kazuhiro
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/746,699
• Time in Patent Office: 1,167 Days
• Field of Search: 365/222, 365/200, 365/230, 365/189, 365/182
• US Class Current: 365/222
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A semiconductor memory circuit which can operate with reduced value of peak currents.

The memory circuit includes two or more memory cell arrays each having a plurality of memory cells and a peripheral circuit for achieving selective access operation is provided for each array. At least a timing signal and its delayed timing signals are generated in response to a control signal. Both of the timing signal and the delayed timing signal are used to enable the peripheral circuits at different timing.

Claims

1. A memory circuit comprising first and second memory cell arrays each including a plurality of memory cells arranged in rows and columns, a first peripheral circuit for operatively accessing said first memory cell array, a second peripheral circuit for operatively accessing said second memory cell array, means for receiving a control signal, means responsive to said control signal for generating a first timing signal, a delay circuit responsive to said first timing signal for generating a delayed second timing signal, means for applying said first and second timing signals to one and the other of said first and second timing signals to one and the other of said first and second peripheral circuits separately, to thereby enable said first and second peripheral circuits in response to said one and the other of said first and second timing signals, respectively.

2. The memory circuit according to claim 1, wherein said first peripheral circuit includes a first row drive circuit for selectively driving one of the rows of said first array in response to said one of said first and second timing signals and said second peripheral circuit includes a second row drive circuit for selectively driving one of the rows of said second array in response to said other of said first and second timing signals and said second peripheral circuit includes a second row drive circuit for selectively driving one of the rows of said second array in response to said other of said first and second timing signals.

3. The memory circuit according to claim 1, wherein said applying means applies said first timing signal to one of said first and second peripheral circuits which is coupled to the memory cell array to be addressed and said second timing signal to the other of said first and second peripheral circuits which is coupled to the memory cell array not to be addressed.

4. A semiconductor memory circuits comprising a plurality of memory cell arrays, each of said arrays including a plurality of selective refresh circuits provided for said arrays, each of said selective refresh circuits operatively refreshing at least one memory cell in each one of said arrays, means receiving a control signal, a timing signal generator responsive to said control signal for generating at least a first timing signal and a second delayed timing signal, means for applying said first timing signal to a part of said selective refresh circuits to thereby enable said part of said selective refresh circuits, and means for applying said second delayed timing signal to another part of said selective refresh circuits to thereby enable said other part of said selective refresh circuits.

5. The memory circuit according to claim 4, in which each of said selective refresh circuits includes a row selection circuit for selecting the rows of each one of said arrays in response to either of said first and second timing signals applied thereto.

6. The memory circuit according to claim 4, wherein each of said selective refresh circuits includes a row drive circuit for selecting the rows and a plurality of sense amplifiers provided for the columns in each array.

7. The memory circuit according to claim 5, wherein said timing signal generator includes means for generating a third timing signal for enabling the sense amplifiers of a part of said arrays associated to said part of said selective refresh circuits and means for generating a fourth timing signal delayed from said third signal, said fourth signal enabling the sense amplifiers of other part of said arrays associated to said other part of said selective refresh circuit.

8. A semiconductor memory circuit comprising first and second memory cell arrays each having word lines, bit lines and a plurality of memory cells coupled between said word lines and said bit lines;

a first word line driver circuit for operatively selecting one of the word lines in said first array;

a second word line driver circuit for operatively selecting on of the word lines in said second array;

means for receiving a control signal;

a timing signal generator for generating a first timing signal and a second timing signal delayed from said first timing signal;

means for applying said first timing signal to one of said first and second word line drives circuits to thereby enable said on of said first and second word line driver circuits; and

means for applying said second timing signal to the other of said first and second word line driver circuits to thereby enable said other of said first and second word line driver circuits.

9. A semiconductor memory circuit comprising first and second memory arrays, each of said first and second arrays including a plurality of word lines, a plurality bit lines and a plurality of memory cells each coupled to each one of said word lines and each one of said bit line;

means for receiving a control signal;

a timing signal generator for generating a first timing signal and a second timing signal which is delayed from said first timing signal in response to said control signal;

a first word line drive circuit for operatively selecting one of the word lines of said first array in accordance with address signals;

a second word line drive circuit for operatively selecting one of the word lines of said second array in accordance with said address signals;

means for applying said first timing signal to said first word line drive circuit thereby to enable said first word line drive circuit; and

means for applying said second timing signal to said second word line drive circuit thereby to enable said second word line drive circuit;

said first and second word line drive circuits including a plurality of selection units each provided for each one of the word lines of said first and second arrays, respectively, each of said selection units of said first word line drive circuit incluidng a logic gate, a source-follower transistor having a gate coupled to an output of said logic, a source coupled to one of the word lines of said first array and a drain supplied with said first timing signal, each of said selection units of said second word line drive circuit including a logic gate, a source-follower transistor having a gate coupled to an output of said logic gate, a source coupled to one of the word lines of said second array and a drain supplied with said second timing signal.

10. The memory circuit according to claim 9, in which each of said logic gates is a NOR circuit.

11. A semiconductor memory circuit comprising a first and second memory arrays, each of said first and second memory arrays including a plurality of word lines, a plurality of bit lines and a plurality of memory cells;

a first word line selection circuit coupled to the word lines of said first memory array for operatively selecting one of the word lines of said frist memory;

a second word line selection circuit coupled to the word lines of said second memory array for operatively selecting one of the word lines of said second memory array;

means for receiving a control signal;

a timing signal generator for generating a first timing signal and a second timing signal delayed from said first timing signal in response to said control signal; and

a timing signal selection circuit coupled to said timing signal generator and having first terminal coupled to said first word line selection circuit and a second terminal coupled to said second word line selection circuit, said timing signal selection circuit being responsive to address information to output said first and second timing signals from said first and second terminals, respectively when said first memory array is to be accessed and to output said first and second timing signals from said second and first terminals, respectively when said second memory array is to be accessed.

12. The memory circuit according to claim 11, further comprising a plurality of first sense amplifiers coupled to the bit lines of said first memory array;

a plurality of second sense amplifiers coupled to the bit lines of said second memory array;

means couled to said first terminal for generating a third timing signal for enabling said first sense amplifiers; and

means coupled to said second terminal for generating a fourth timing signal for enabling said second sense amplifiers.

13. The memory circuit according to claim 11, in which said timing signal selection circuit includes a first input node to which said first timing signal is applied;

a second input node to which said second timing signal is applied;

a first field effect transistor coupled between said first input node and said first terminal;

a second field effect transistor coupled between said first input node and said second terminal;

a third field effect transistor coupled between said second input node and said first terminal;

a fourth field effect transistor coupled between said second input node and said second terminal;

means for simultaneously rendering said first and fourth transistors conductive when said first memory array is to be accessed; and

means for simultaneously rendering said second and third transistors conductive when said second memory array is to be accessed.