Integrated switched-capacitor filter with improved frequency characteristics

• US 4,769,612 A
• Filed: 10/15/1987
• Issued: 09/06/1988
• Est. Priority Date: 11/18/1983
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Takatori, Hiroshi, Suzuki, Toshiro, Tamakoshi, Masashi
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Callahan, Timothy P.
• Application Number:
  US07/110,574
• Time in Patent Office: 327 Days
• Field of Search: 328/167, 328/151, 328/155, 307/520, 307/521, 307/491, 333/173, 333/213, 330/9, 330/107, 330/109
• US Class Current: 327/554
• CPC Class Codes: H03H 19/004 Switched capacitor networks

Abstract

A switched-capacitor filter constituted in the form of a semiconductor integrated circuit has an input circuit which consists of at least one noninversion-type switched-capacitor and at least two inversion-type switched-capacitors that are connected in parallel with each other. The two inversion-type switched-capacitors have different writing timings and reading timings relative to each other. With this setup, capacitances of the switched-capacitors need not be extremely increased even when it is desired to maintain a zero-point frequency of the filter at a very low value. Further, there is no need of providing a circuit such as sample holding circuit which requires extra area and consumes additional electric power.

Claims

1. A semiconductor integrated circuit comprising:

an input node for receiving an input signal;

operational amplifier means having an input terminal and an output terminal;

a first inversion-type switched-capacitor and a second inversion-type switched-capacitor that are coupled in parallel between said input node and said input terminao, wherein said first inversion-type switched-capacitor includes a first capacitor and said second inversion-type switched-capacitor includes a second capacitor having a substantially equal capacitance to said first capacitor, and wherein a charge proportional to the input signal is written in each of said first and second capacitors in a writing operation thereof, and wherein each of said first and second capacitors provides a charge of opposite polarity to that written therein to said input terminal in a read-out operation thereof;

a first noninversion-type switched-capacitor and a second noninversion-type switched-capacitor that are coupled in parallel between said input node and said input terminal, wherein said first noninvernsion-type swithced-capacitor includes a third capacitor and said second noninvernsion-type switched-capacitor includes a fourth capacitor having a substantially equal capacitance to said third capacitor, and wherein a charge proportional to the input signal is written into each of said third and fourth capacitors in a writing operation thereof, and wherein each of said third and fourth capacitors provides a charge of the same polarity as that written therein to said input terminal in a read-out operation thereof; and

a third noninvernsion-type switched-capacitor coupled between said input terminal and said output terminal, said third noninvernsion-type switched-capacitor including a fifth capacitor, wherein a writing and a read-out operation of said fifth capacitor is executed at a frequency having a predetermined period,

wherein said first and socond inversion-type switched-capacitors and said first and second noninvernsion-type switched-capacitors are controlled so that read-out operation of said first, second, third and fourth capacitors is executed at a frequency having a different period from said predetermined period, so that each writing operation of said first, second, third and fourth capacitors is executed at a frequency having a different period from said predetermined period, so that the writing operation of said first capacitor is executed at a different timing from that of said second capacitor, so that the writing operation of said third capacitor is executed at a different timing from that of said fourth capacitor, so that the writing operation of said first capacitor is executed at a substantially equal timing to that of said third capacitor, so that the writing operation of said second capacitor is executed at a substantially equal timing to that of said fourth capacitor, so that the read-out operation of said first capacitor is executed at a substantially equal timing to that of said fourth capacitor, so that the read-out operation of said second capacitor is executed at a substantially equal timing to that of said third capacitor, and so that each read-out operation of said third and fourth capacitors is executed at a substantially equal timing to the writing operation thereof.

2. A semiconductor integrated circuit according to claim 1, wherein said first and second inversion-type switched-capacitors and said first and second noninversion-type switched-capacitors are controlled so that each read-out operation of said first, second, third and fourth capacitors is executed at a frequency having a period which is substantially two times as long as said predetermined period, and so that each writing operation of said first, second, third and fourth capacitors is executed at a frequency having a period which is substantially two times as long as said predetermined period.

3. A semiconductor integrated circuit comprising:

an input node for receiving an input signal;

operational amplifier means having an input terminal and an output terminal;

a first inversion-type switched-capacitor and second inversion-type switched-capacitor that are coupled in parallel between said input node and said input terminal, wherein said first inversion-type switched-capacitor includes a first capacitor and said second inversion-type switched-capacitor includes a second capacitor having a substantially equal capacitance to said first capacitor, and wherein a charge proportional to the input signal is written into each of said first and second capacitors in a writing operation thereof, and wherein each of said first and second capacitors provides a charge of opposite polarity to that written therein to said input terminal in a read-out operation thereof; and

a first noninversion-type switched-capacitor coupled between said input node and said input terminal, said first noninversion-type switched-capacitor including a third capacitor, wherein a charge proportional to the input signal is written into said third capacitor in a writing operation thereof and said third capacitor provides a charge of the same polarity as that written therein to said input terminal in a read-out operation thereof, wherein said writing operation of said third capacitor is executed at a substantially equal timing to the read-out operation thereof, and wherein the read-out operation of said third capacitor is exeucted at a frequency having a predetermined period,

wherein said first and second inversion-type switched-capacitors are controlled so that read-out operation of said first and second capacitors is executed at a frequency having a different period from said predetermined period, so that each writing operation of said first and second capacitors is executed at a frequency having a different period from said predetermined period, so that the writing operation of said first capacitor is executed at a different timing from that of said second capacitor, and so that the read-out operation of said first capacitor is executed at a different timing from that of said second capacitor.

4. A semiconductor integrated circuit according to claim 3, wherein said first and second inversion-type switched-capacitors are controlled so that the read-out operation of said first capacitor is executed at a substantially equal timing to the writing operation of said second capacitor, and so that the writing operation of said first capacitor is executed at a substantially equal timing to the read-out operation of said second capacitor.

5. A semiconductor integrated circuit according to claim 4, wherein said first and second inversion-type switched-capacitors are controlled so that each read-out operation of said first and second capacitors is executed at a frequency having a period which is substantially two times as long as said predetermined period, and so that each writing operation of said first and second capacitors is executed at a frequency having a period which is substantially two times as long as said predetermined period.

6. A semiconductor integrated circuit according to claim 5, further comprising a second noninversion-type switch-capacitor coupled between said input terminal and said output terminal, said second noninversion-type switched-capacitor including a fourth capacitor, wherein a writing and a read-out operation of said fourth capacitor is executed at a frequency having said predetermined period.

7. A semiconductor integrated cirucit according to claim 6, further comprising a fifth capacitor coupled between said input terminal and said output terminal.

8. A semiconductor integrated circuit comprising:

an input node for receiving an input signal;

operational amplifier means having an input terminal and an output terminal;

a first capacitor coupled between said input terminal and said output terminal;

a first inversion-type switched-capacitor and a second inversion-type switched-capacitor that are coupled in parallel between said input node and said input terminal, wherein said first inversion-type switched-capacitor includes a second capacitor and said second inversion-type switched-capacitor includes a third capacitor having a substantially equal capacitance to said second capacitor, and wherein a charge proportional to the input signal is written into each of said second and third capacitors in a writing operation thereof, and wherein each of said second and third capacitors provides a charge of opposite polarity to that written therein to said input terminal in a read-out operation thereof; and

a noninversion-type switched-capacitor coupled between said input node and said input terminal, said noninversion-type switched-capacitor including a fourth capacitor, wherein a charge proportional to the input signal is written into said fourth capacitor in writing operation thereof, and wherein said fourth capacitor provides a charge of the same polarity as that written therein to said input terminal in a read-out operation thereof, wherein said writing operation of said fourth capacitor is executed at a substantially equal timing to the read-out operation thereof, and wherein the read-out operation of said fourth capacitor is executed at a frequency having a predetermined period,

wherein said first and second invernsion-type switched-capacitors are controlled so that each read-out operation of said second and third capacitors is executed at a frequency having a different period from said predetermined period, so that each writing operation of said second and third capacitors is executed at a frequency having a different period from said predetermined period, so that the wrwiting operation of said second capacitor is executed at a different timing from that of said third capacitor, and so that the read-out operation of said second capacitor is executed at a different timing from that of said third capacitor.

9. A semiconductor integrated circuit according to claim 8, wherein said first and second inversion-type switched-capacitors are controlled so that the read-out operation of said second capacitor is executed at a substantially equal timing to the writing operation of said third capacitor, and so that the writing operation of said second capacitor is executed at a substantially equal timing to the read-out operation of said third capacitor.

10. A semiconductor integrated circuit according to claim 9, wherein said first and second inversion-type switched-capacitors are controlled so that each read-out operation of said second and third capacitors is executed at a frequency having a period which is substantially two times as long as said predetermined period, and so that each writing operation of said second and third capacitors is executed at a frequency having a period which is substantially two times as long as said predetermined period.

11. A semiconductor integrated circuit comprising:

an input node for receiving an input signal;

operational amplifier means having an input terminal and an output terminal;

a first inversion-type switched-capacitor and a second inversion-type switched-capacitor that are coupled in parallel between said input node and said input terminal, wherein said first inversion-type switched-capacitor includes a first capacitor and a first pair of switches, wherein said second inversion-type switched-capacitor includes a second pair of switches and a second capacitor having a substantially equal capacitance to said first capacitor, and wherein a charge proportional to the input signal is written in each of said first and second capacitors when said first and second pairs of switches are in a first predetermined switching condition in a writing operation of said first and second capacitors, and wherein each of said first and second capacitors provides a charge of opposite polarity to that written therein to said input terminal when said first and second pairs of switches are in a second predetermined switching condition in a read-out operation of said first and second capacitors;

a first noninversion-type switched-capacitor and a second noninversion-tyep switched-capacitor that are coupled in parallel between said input node and said input terminal, wherein said first noninversion-type switched-capacitor includes a third capacitor and a third pair of switches and said second noninversion-type switch-capacitor includes a fourth pair of switches and a fourth capacitor having a substantially equal capacitance to said third capacitor, and wherein a charge proportional to the input signal is written into each of said third and fourth capacitors when said third and fourth pairs of switches are in a first predetermined switching condition in a writing operation of said third and foruth capacitors, and wherein each of said third and fourth capacitors provides a charge of the same polarity as that written therein to said input terminal when said third and fourth pairs of switches are in said first predetermined switching condition in a read-out operation of said third and fourth capacitors; and

a third noninversion-type switched capacitor coupled between said input terminal and said output terminal, said third noninversion-type switched-capacitor including a fifth capacitor and a fifth pair of switches, wherein a writing and a read-out operation of said fifth capacitor is executed by operating said fifth pair of switches at a frequency having a predetermined period,

wherein switching operations of said first and second pairs of switches of said first and second inversion-type switch-capacitors and switching operations of said third and fourth pairs of switches of said first and second noninversion-type switched-capacitors are controlled so that read-out operation of said first, second, third and fourth capacitors is executed at a frequency having a different period from said predetermined period, so that each writing operation of said first, second, third and fourth capacitors is executed at a frequency having a different period from said predetermined period, so that the writing operation of said first capacitor is executed at a different timing from that of said second capacitor, so that the writing operation of said third capacitor is executed at a different timing from that of said fourth capacitor, so that the writing operation of said first capacitor is executed at a substantially equal timing to that of said third capacitor, so that the writing operation of said second capacitor is executed at a substantially equal timing to that of said fourth capacitor, so that the read-out operation of said first capacitor is executed at a substantially equal timing to that of said fourth capacitor, so that the read-out operation of said second capacitor is excuted at a substantially equal timing to that of said third capacitor, so that each read-out operation of said third and fourth capacitors is executed at a substantially equal timing to the writing operation thereof, and so that each read-out operation of said first, second, third and fourth capacitors is executed at a frequency having a period which is substantially two times as long as said predetermined period, and so that each writing operation of said first, second, third and fourth capacitors is executed at a frequency having a period which is substantially two times as long as said predetermined period.

12. A semiconductor integrated circuit according to claim 11, wherein each of said first, second, third, fourth and fifth pairs of switches is comprised of a pair of field-effect transistors.

13. A semiconductor integrated circuit according to claim 11, further comprising a sixth capacitor coupled between said input terminal and said output terminal.

14. A semiconductor integrated circuit comprising:

an input node for receiving an input signal;

operational amplifier means having an input terminal and an output terminal;

a first inversion-type switched-capacitor and a second inversion-type switched-capacitor that are coupled in parallel between said input node and said input terminal, wherein said first inversion-type switch-capacitor includes a first capacitor and a first pair of switches, wherein said second inversion-type switched-capacitor includes a second pair of switches and a second capacitor having a substantially equal capacitance to said first capacitor, and wherein a charge proportional to the input signal is written into each of said first and second capacitors when said first and second pairs of switches are in a first predetermined switching condition in a writing operation of said first and second capacitors, and wherein each of said first and second capacitors provides a charge of opposite polarity to that written therein to said input terminal when said first and second pairs of switches are in a second predetermined switching condition in a read-out operation of said first and second capacitors; and

a first noninversion-type switched-capacitor coupled between said input node and said input terminal, said first noninversion-type switched-capacitor including a third capacitor and a third pair of switches, wherein a charge proportional to the input signal is written into said third capacitor when said third pair of switches is in a first predetermined switching position during a writing operation of said third capacitor, and wherein said third capacitor provides a charge of the same polarity as that written therein to said input terminal when said third pair of switches are in said first predetermined switching position in a read-out operation of said third capacitor, wherein said writing operation of said third capacitor is executed at a substantially equal timing to the read-out operation thereof, and wherein the read-out operation of said third capacitor is executed at a frequency having a predetermined period,

wherein switching operations of said first and second pairs of switches of said first and second inversion-type switched-capacitors are controlled so that each read-out operation of said first and second capaciotrs is executed at a frequency having a different period from said predetermined period, so that each writing operation of said first and second capacitors is executed at a frequency having a different period from said predetermined period, so that the writing operation of said first capacitor is executed at a different timing form that of said second capacitor, so that the read-out operation of said first capacitor is executed at a different timing form that of said second capacitor, so that the read-out operation of said first capacitor is executed at a substantially equal timing to the writing operation of said second capacitor, so that the writing operation of said first capacitor is executed at a substantially equal timing to the read-out operation of said second capacitor, so that each read-out operation of said first and second capacitors is executed at a frequency having a period which is substantially two times as long as said predetermined period, and so that each writing operation of said first and second capacitors is executed at a frequency having a period which is substantially two times as long as said predetermined period,

said semiconducotr integrated circuit further comprising a second noninversion-type swiwtched-capacitor coupled between said input terminal and said output terminal, said second noninversion-type switched-capacitor including a fourth capacitor and a fourth pair of switches, wherein a writing and a read-out operation of said fourth capacitor is executed by operating said fourth pair of switches at a frequency having said predetermined period.

15. A semiconductor integrated circuit according to claim 14, further comprising a fifth capacitor coupled between said input terminal and said output terminal.

16. A semiconductor integrated circuit according to claim 14, wherein each of said first, second, third and fourth pairs of switches is comprised of a pair of field-effect transistors.

17. A semiconductor integrated circuit comprising:

an input node for receiving an input signal;

operational amplifier means having an input terminal and an output terminal;

a first capacitor coupled between said input terminal and said output terminal;

a first inversion-type switched-capacitor and a second inversion-type switched-capacitor that are coupled in parallel between said input node and said input terminal, wherein said first inversion-type switched-capacitopr includes a second capacitor and a first pair of switches, wherein said second inversion-type switched-capacitor includes a second pair of switches and a third capacitor having a substantially equal capacitance to said second capacitor, and wherein a charge proportional to the input signal is written into each of said second and third capacitors when said ifrst and second pairs of switches are in a first predetermined switching condition in a writing operation of said second and third capacitors, and wherein each of said second and third capacitors provides a charge of opposite polarity to that written therein to said input terminal when said first and second pairs of switches are in a second predetermined switching position in a read-out operation of said second and third capacitors;

a noninversion-type switched-capacitor coupled between said input node and said input terminal, said noninversion-type switched-capacitor including a fourth capacitor and a third pair of switches, wherein a charge proportional to the input signal is written into said fourth capacitor when said third pair of switches is in a first predetermined switching position in a writing operation of said fourth capaciotr, and wherein said fourth capacitor provides a charge of the same polarity as that written therein to said input terminal when said third pair of switches are in said first predetermined switching position in a read-out operation of said fourth capacitor, wherein said writing operation of aid fourth capaciotr is executed at a substantially equal timing to the read-out operation thereof, and wherein the read-out operation of said fourth capacitor is excuted at a frequency having a predetermined period,

wherein switching operations of said first and second pairs of switches of said first and second inversion-type switched-capaciotrs are controlled so that each read-out operation of said second and third capaciotrs is executed at a frequency having a different period from said predetermined period, so that each writing operation of said second and third capacitors is excuted at a frequency having a different period from said predetermined period, so that the writing operation of said second capacitor is executed at a different timing from that of said third capacitor, so that the read-out operation of said second capacitor is executed at a different timing from that of said third capacitor, so that the read-out operation of said second cpaacitor is executed at a substantially equal timing to the writing operation of said third capacitor, so that the writing operation of said second capacitor is executed at a substantially equal timing to the read-out operation of said third capacitor, so that each read-out operation of said second and third capaciotrs is executed at a frequency having a period which is substantially two times as long as said predetermined period, and so that each writing operation of said second and third capaciotrs is executed at a frequency having a period which is substantially two times as long as said predetermined period.

18. A semiconductor integrated circuit according to claim 17, wherein each of said first, second and third pairs of switches is comprised of a pair of field-effect transistors.