Process of attaching a die to a substrate using gold/silicon seed

• US 4,771,018 A
• Filed: 03/19/1987
• Issued: 09/13/1988
• Est. Priority Date: 06/12/1986
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bhattacharyya, Bidyut K., Tosaya, Eric S.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Bunch, William D.
• Application Number:
  US07/027,638
• Time in Patent Office: 544 Days
• Field of Search: 29/589, 29/588, 29/580, 29/583, 29/840, 29/843, 357/71, 357/81, 357/67, 357/80, 228/208, 228/209, 228/210, 228/238, 437/180, 437/209, 437/190, 437/245, 437/246, 437/247, 148/DIG. 12, 148/DIG.62
• US Class Current: 228/123.1
• CPC Class Codes: B23K 2035/008 at least one of the workpieces being of silicium
• CPC Class Codes: B23K 35/007 at least one of the workpieces being of copper or another noble metal
• CPC Class Codes: B23K 35/3013 Au as the principal constituent
• CPC Class Codes: H01L 2224/83101 as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/83805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/0132 Binary Alloys
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/07802 not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: Y10S 148/012 : Bonding, e.g. electrostatic for strain gauges
• CPC Class Codes: Y10S 148/062 : Gold diffusion
• CPC Class Codes: Y10T 29/49149 : by metal fusion bonding

Abstract

An improved method for eutectically bonding a silicon wafer onto a gold preform is described. A gold/silicon seed is placed on a pure gold preform. Then a die is placed onto the pure gold preform and the gold/silicon seed, wherein the seed acts as a catalyst to form an eutectic bond.

Claims

1. A method for bonding a semiconductor die having a planar size of at least 0.200×

0.200 inches. onto a dielectrically insulated body, said die having a silicon chip and an intermediate barrier metal comprising the steps of;

(a) depositing a gold layer on said dielectrically insulated body;

(b) placing a pure gold preform on said gold layer;

(c) placing a gold/silicon seed comprised of a gold/silicon eutectic alloy, having a lower percentage of silicon than gold, on said deposited gold preform, wherein said gold/silicon seed contacts approximately 10-20% of a surface of said pure gold preform;

(d) placing said die on said gold/silicon seed such that said intermediate barrier metal contacts said gold/silicon seed;

(e) heating said gold preform and gold/silicon seed; and

(f) scrubbing gently said die on said gold/silicon seed at a bonding temperature of approximately 400°

C. such that said gold/silicon seed melts and forms a liquid layer which acts as a catalyst for further transfer of thermal energy from said pure gold preform to said die;

continued scrubbing of said die causes silicon atoms from said chip to penetrate said intermediate barrier metal and combine with said gold/silicon liquid layer wherein said percentage of silicon increases causing eutectic melting point of said gold/silicon layer to decrease;

said scrubbing is initiated at a eutectic melting point of gold/silicon having an initial value greater than the minimum melting temperature of gold/silicon, but continued scrubbing causes said eutectic melting point to decrease in value until said minimum value is reached at which time further reaction of silicon from said chip increases percentage of silicon in comparison to gold causing said eutectic melting point to increase until said eutectic melting point reaches said bonding temperature, wherein silicon atoms in said die migrate across said intermediate barrier metal to said gold preform and form a gold/silicon eutectic bond.

2. The method as defined in claim 1, wherein said intermediate barrier metal is comprised of chromium and said bonding is substantially independent of thickness of said intermediate metal.

3. The method as defined in claim 2, wherein said die having a second gold layer deposited on said intermediate barrier metal, such that said second gold layer makes contact with said gold/silicon preform.