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Method of making integrated circuit with pair of MOS field effect transistors sharing a common source/drain region

  • US 4,772,568 A
  • Filed: 05/29/1987
  • Issued: 09/20/1988
  • Est. Priority Date: 05/29/1987
  • Status: Expired due to Term
First Claim
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1. In a method of making an integrated circuit device including a body of semiconducting material of a first conductivity type having a planar surface and a pair of MOSFETs each of which has a source or drain region which shares a common active region with the other, the steps comprising:

  • (a) forming a first insulated gate on said planar surface;

    (b) forming highly doped first and second regions, and a third region of of of either conductivity type in said body, the first, second, and third regions being spaced apart and extending inwardly from said planar surface, said first and second regions being spaced to define a first channel region therebetween that is in substantial alignment with said first gate;

    (c) forming a continuous layer of monocrystalline silicon using said second and third regions as nucleation sites wherein one portion of said continuous layer extends from said second region and another portion extends from said third region, said layer of single crystalline silicon being of the same conductivity type as said second and third regions;

    (d) forming a second insulated gate on a portion of said continuous layer of monocrystalline silicon other than said one portion extending from said second region; and

    (e) forming highly doped fourth and fifth regions of conductivity type opposite that of said first, second, and third regions in said layer of monocrystalline silicon spaced to define a second channel region therebetween that is in substantial alignment with said second gate,wherein said fourth region is in said one portion of said layer of monocrystalline silicon that extends from said second region.

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