Method of making integrated circuit with pair of MOS field effect transistors sharing a common source/drain region

• US 4,772,568 A
• Filed: 05/29/1987
• Issued: 09/20/1988
• Est. Priority Date: 05/29/1987
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: General Electric Company
• Inventors: Jastrzebski, Lubomir L.
• Primary Examiner(s): Ozaki, George T.
• Application Number:
  US07/055,220
• Time in Patent Office: 480 Days
• Field of Search: 437/41, 437/89, 437/156, 437/913, 437/915, 437/34
• US Class Current: 438/153
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 29/78639 with a drain or source connected to a bulk conducting substrate
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

The present invention is a method of making an integrated circuit device including a pair of MOSFETs each of which has a source or drain region which shares a common active region with the other. The method includes forming an epitaxial layer from nucleation sites, one of which is the source or drain region of the first MOSFET. The second MOSFET is then formed in the epitaxial layer so that one of the source or drain regions extends from one of the nucleation sites.

Claims

1. In a method of making an integrated circuit device including a body of semiconducting material of a first conductivity type having a planar surface and a pair of MOSFETs each of which has a source or drain region which shares a common active region with the other, the steps comprising:

(a) forming a first insulated gate on said planar surface;

(b) forming highly doped first and second regions, and a third region of of of either conductivity type in said body, the first, second, and third regions being spaced apart and extending inwardly from said planar surface, said first and second regions being spaced to define a first channel region therebetween that is in substantial alignment with said first gate;

(c) forming a continuous layer of monocrystalline silicon using said second and third regions as nucleation sites wherein one portion of said continuous layer extends from said second region and another portion extends from said third region, said layer of single crystalline silicon being of the same conductivity type as said second and third regions;

(d) forming a second insulated gate on a portion of said continuous layer of monocrystalline silicon other than said one portion extending from said second region; and

(e) forming highly doped fourth and fifth regions of conductivity type opposite that of said first, second, and third regions in said layer of monocrystalline silicon spaced to define a second channel region therebetween that is in substantial alignment with said second gate,

wherein said fourth region is in said one portion of said layer of monocrystalline silicon that extends from said second region.

2. The method as set forth in claim 1 wherein said body of semiconducting material has a monocrystalline portion within each of said second and third regions at said planar surface.

3. The method set forth in claim 2 wherein step (c) includes forming said continuous layer of monocrystalline silicon by means of epitaxial lateral overgrowth.

4. The method set forth in claim 3 wherein said fourth region extends into said continuous layer of monocrystalline silicon a distance of less than the thickness of said continuous layer.

5. The method set forth in claim 4 wherein said continuous layer of monocrystalline silicon is formed to a thickness of about 500 microns.