Digital electronic recorder/player

• US 4,772,873 A
• Filed: 08/30/1985
• Issued: 09/20/1988
• Est. Priority Date: 08/30/1985
• Status: Expired due to Term

• Current Assignee: TranSafe Corp (Trinity Industries Incorporated)
• Original Assignee: Digital Recorders Inc. (Clever Devices, Ltd.)
• Inventors: Duncan, Virgil D.
• Primary Examiner(s): Sloyan, T. J.
• Application Number:
  US06/772,132
• Time in Patent Office: 1,117 Days
• Field of Search: 340/347 SH, 340/347 M, 340/347 AD, 340/347 DA, 364/572, 364/576, 364/178, 364/179, 364/724, 358/138, 381/31
• US Class Current: 341/110
• CPC Class Codes: G09B 5/04 with audible presentation of the material to be studied sound recording or reproducing G11B
• CPC Class Codes: G11C 2207/16 Solid state audio deprecated, only for historical reasons, G06F3/16, G11B
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

The invention is a digital record/playback apparatus including an input digital filter, and A/D converter, a solid state memory, a D/A converter and an output digital filter. The entire system is driven off a single clock source which allows the frequent response of the filters to be modified simultaneous with the sampling frequency of the A/D and D/A converter. This allows the record/playback apparatus to record low frequency signals, such as medical data, as well as relatively high frequency signals such as voice, by simply changing the frequency of the clock source. In addition, the apparatus includes an expandable memory which allows recording of up to one hour or more of program material.

Claims

1. A digital recorder comprising:

an input digital filter means for receiving an input analog signal and for high frequency limiting said input analog signal;

an analog to digital converter coupled to said input digital filter means for converting said high frequency limited analog input signal to a digital signal;

a memory means coupled to said analog to digital converter for storing said digital signal;

a digital to analog converter coupled to said memory means for converting said digital signal to an output analog signal;

an output digital filter means coupled to said digital to analog converter for filtering said output analog signal;

a clock source providing a first clocking frequency signal; and

a frequency divider means including;

an even fequency divider having an input for receiving said first clocking frequency signal and having a plurality of outputs, each output providing a clocking frequency signal having a frequency substantially equal to the frequency of the first clocking frequency signal divided by an even integer;

a pair of diodes having respective cathodes connected to respective ones of said plurality of said plurality of outputs, and having commonly connected anodes connected to a differenct one of said plurality of outputs; and

a resistor connectable between a source of voltage and said commonly connected anodes;

wherein said diodes and said resistor cause said even frequency divider to skip all individual 1'"'"'s appearing on said output connected to said anodes to accomplish odd frequency division and to provide a second clocking frequency signal synchronized with said first clocking frequency signal and having a frequency substantially equal to said first clocking frequency divided by an odd integer;

said first clocking frequency signal driving said input digital filter means and said output digital filter means, and said second clocking frequency signal driving said analog to digital convertor, said memory means and said digital to analog converter.

2. The digital recorder according to claim 1, wherein said clock source includes a clock means operating at said first clocking frequency to provide said first clocking frequency signal, said clock means being located on board one of said digital filter means.

3. The digital recorder according to claim 2, wherein the ratio of a high frequency response of said digital filters to the first clocking frequency is approximately 50 to 1.

4. The digital recorder according to claim 1, wherein said memory is solid state memory.

5. The digital recorder according to claim 4, wherein said solid state memory is CMOS memory.

6. The digital recorder according to claim 5, wherein said solid state memory is an expandable memory.