Thin film FET doped with diffusion inhibitor

• US 4,772,927 A
• Filed: 10/23/1986
• Issued: 09/20/1988
• Est. Priority Date: 10/23/1985
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Saito, Ryuichi, Momma, Naohiro
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Lamont, John
• Application Number:
  US06/922,347
• Time in Patent Office: 698 Days
• Field of Search: 357/23.7, 357/23.1, 357/59, 357/63, 357/64, 357/42, 437/21, 437/24
• US Class Current: 257/66
• CPC Class Codes: H01L 21/32155 Doping polycristalline - or amorphous silicon layers
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

The present invention relates to a semiconductor device including a MOS transistor which is formed with a source region, a drain region and a channel region by the use of polycrystalline silicon, and a method of manufacturing the semiconductor device. Ions of carbon, oxygen or/and nitrogen are introduced into a polycrystalline silicon layer over the whole area thereof, and restrain conductive ions in the source and drain regions from diffusing into the channel region.

Claims

1. A semiconductor device having a MOS transistor element which is formed with a source region, a drain region and a channel region in a polycrystalline silicon layer on a semiconductor body, characterized in that said source region, drain region and channel region are all formed of polycrystalline silicon, that a conductive impurity is contained in said source region and drain region, and that at least one species of ions selected from the group consisting of oxygen, nitrogen and carbon ions are contained in said source region, drain region and channel region in order to restrain said conductive impurity from diffusing into said channel region.

2. A semiconductor device as defined in claim 1, wherein the at least one species of ions selected from the group consisting of oxygen, nitrogen and carbon are contained in said source region, drain region and channel region such that the grain boundaries of the polycrystalline silicon respectively are partly formed with at least one of silicon oxide, silicon nitride and silicon carbide.

3. A semiconductor device as defined in claim 1, wherein the concentration of the at least one species of ions contained in said source region, drain region and channel region is 10¹⁹ -10²² atoms/cm³.

4. A semiconductor device as defined in claim 1, wherein said at least one species of ions is contained at a relatively low concentration in the channel region and a relatively high concentration in the source and drain regions as compared to the concentration in the channel region.

5. A semiconductor device as defined in claim 4, wherein the concentration of the at least one species of ions contained in the channel region is 10¹⁹ -10²⁰ atoms/cm³, the concentration of the at least one species of ions contained in the source and drain regions being 10¹⁹ -10²² atoms/cm³.

6. A semiconductor device as defined in claim 1, the device further including a gate electrode, spaced from the channel region in the polycrystalline silicon layer via a gate insulating film.

7. A semiconductor device as defined in claim 6, wherein said gate electrode has a width of at most 2 μ

m.

8. A semiconductor device as defined in claim 6, wherein said semiconductor body has source and drain regions formed therein, with a channel region formed in the semiconductor body extending between the source and drain regions, the device further comprising a gate electrode spaced via a gate insulating film from the channel region in the semiconductor body.

9. A semiconductor device as defined in claim 8, wherein the gate electrode spaced from the channel region in the semiconductor body and the gate electrode spaced from the channel region in the polycrystalline silicon film is a common gate electrode, extending between said semiconductor body and said polycrystalline silicon film.

10. A semiconductor device as defined in claim 8, wherein the conductive impurity contained in the source and drain regions in the polycrystalline silicon layer are of a first conductivity type, and the source and drain regions formed in the semiconductor body contain a conductive impurity of a second conductivity type opposite the first conductivity type.

11. A semiconductor device as defined in claim 1, wherein all of said polycrystalline silicon layer contains said at least one species of ions.