Dual block still video compander processor
First Claim
1. A still video transceiver, comprising:
- a digital video frame store memory adaptable to store plural blocks of video data;
a dual port memory having first and second memory ports;
means for fetching dual blocks of video data from said frame store memory and for loading said dual blocks into said dual port memory;
digital signal processor means for accessing through said first memory port and discrete cosine transforming each one of said dual blocks to generate a corresponding block of transform coefficients;
data processing means for accessing through said second port and compressing each block of said transform coefficients to generate a batch of compressed transform coefficients therefrom, whereby said digital signal processing means and said data processing means may operate virtually simultaneously upon different respective ones of said dual blocks.
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Abstract
A video transceiver includes a compressor which grabs a pair of blocks of image data from a video frame store and loads them into a dual port memory. A first processor, working through one of the dual ports, performs a portion of an image compression algorithm, while a second processor, working through a second one of the dual ports, performs the remainder of the compression algorithm on each one of the two pairs of blocks, both processors operating in parallel to speed up the entire process. A key word in each block is changed in accordance with each step, so that each of the two processors is prevented from grabbing the wrong one of the two blocks from the dual port memory. The resulting compressed data is queued in a temporary buffer, from which it is returned to another portion of the video frame store in serial fashion, rather than block, in preparation for serial transmission.
70 Citations
21 Claims
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1. A still video transceiver, comprising:
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a digital video frame store memory adaptable to store plural blocks of video data; a dual port memory having first and second memory ports; means for fetching dual blocks of video data from said frame store memory and for loading said dual blocks into said dual port memory; digital signal processor means for accessing through said first memory port and discrete cosine transforming each one of said dual blocks to generate a corresponding block of transform coefficients; data processing means for accessing through said second port and compressing each block of said transform coefficients to generate a batch of compressed transform coefficients therefrom, whereby said digital signal processing means and said data processing means may operate virtually simultaneously upon different respective ones of said dual blocks. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 21)
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11. In a video transceiver including a frame store memory having an image buffer for storing uncompressed image data and a compressed buffer for storing compressed image data, said video transceiver adapted to receive and transmit compressed video data over an external channel in a receive mode and a transmit mode, respectively, a parallel image processor comprising:
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a dual port memory having first and second ports and means for storing rectangular blocks of video data obtained from said frame store memory and means for storing key values associated with each one of said pair of blocks; data processing means acting through one of said first and second ports for grabbing a pair of blocks from either of said image buffer or said compressed image buffer and storing said pair of blocks in said dual port memory, and changing said key values to a first value; transforming means acting through said first port for transforming, in accordance with a discrete cosine transform algorithm, one of said blocks stored in said dual port memory to generate a block of transform coefficients therefrom; and encoding means acting through said second port for minimum redundancy encoding the other of said blocks stored on said dual port memory to generate a corresponding batch of compressed transformed coefficients, and then changing the corresponding one of said key values to a second value, wherein said encoding means and said transforming means are each responsive, whenever one of said location values equals a respective one of said first and second values, for accessing the corresponding one of said two blocks in said dual port memory, whereby said transforming means and said encoding means are mutually prevented from accessing out of order one of said blocks from said dual port memory. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification