Apparatus for monitoring and analyzing large data blocks on a computer channel

• US 4,773,003 A
• Filed: 10/17/1985
• Issued: 09/20/1988
• Est. Priority Date: 10/17/1985
• Status: Expired due to Fees

• Current Assignee: Technologies, Inc. (APi Group Corp.)
• Original Assignee: Technology 80, Inc. (ACS Motion Control Ltd.)
• Inventors: Hauge, Trygve A.
• Primary Examiner(s): Zache, Raulfe B.
• Assistant Examiner(s): Phung, Danh T.
• Application Number:
  US06/788,394
• Time in Patent Office: 1,069 Days
• Field of Search: 364/178, 364/200 MS File, 364/ 900 MS File
• US Class Current: 714/46
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 11/3485 for I/O devices
• CPC Class Codes: G06F 11/349 for interfaces, buses

Abstract

A channel analyzer system has circuits for passive coupling to individual signal lines on a computer data channel, and for monitoring the data passed thereover, with logic circuits having preselectable capability for recognizing transmitted data of interest for further analysis. The system further includes a large storage capability for retaining preselected amounts of data, examining blocks of data so collected and recorded, labeling data samples with an identifier; displaying selected portions of the samples, including representative values signifying the data content and preselected signal line changes of interest, data channel activity prior to and subsequent to the preselected signal line event which is of interest; and displaying the same for providing a visualized summary of activity of a computer channel according to the protocols defined for the channel activity.

Claims

1. A system for monitoring digital communication lines and for detecting predetermined signals transmitted over the digital communication lines and for recording such signals and organizing groups of such signals into a systematic presentment form and displaying the presentment form for viewing by an operator, comprising

(a) a plurality of channel interface circuits, each circuit having an input means for electrical coupling to a digital communication line, and means, connected to said input means, for detecting signal and voltage transitions, output means, connected to said means for detecting signal and voltage transitions, for generating an output signal;

(b) a cache memory having an input register connected to all of said channel interface circuit output means, and having an addressable memory coupled to said input register for receiving and storing data received therefrom, and having an output register coupled to said addressable memory for receiving stored data therefrom;

(c) a first-in, first-out (FIFO) register bank having a first register coupled to said cache memory output register, and having a plurality of further registers coupled in sequential transfer operation to said first register and having an output register coupled to the last of said further registers to receive a last sequential transfer of data first received by said first register;

(d) an addressable large store memory coupled to said FIFO output register, including means for storing in sequential addresses data received from said FIFO output register;

(e) a programmable digital computer coupled to said large store memory, said computer having means for addressing said large store memory and for transferring data from said large store memory to said computer, and said compartment having means for systematically organizing said data into a presentment form wherein said signal voltage transitions are explicitly identified; and

(f) a visual display device connected to said digital computer, including means for receiving said systematically organized data, means for displaying said data presentment form, and means for displaying said explicitly identified voltage transitions.

2. The system of claim 1, wherein said cache memory further comprises a first activation circuit coupled to said pluralilty of channel interface circuits, said circuit having means for generating a first activation signal in response to said interface circuits output signals;

an incremental write counter coupled to receive said first activation signal, including means for generating an incrementally increased write count output value; and

an addressing means coupled to receive said write count output value and for addressing said addressable memory in response thereto.

3. The system of claim 2, wherein said cache memory further comprises a second activation circuit having an input signal line, said second activation circuit having means for generating a second activation signal in response to a received signal on said input signal line;

an incremental read counter coupled to receive said second activation signal, including means for generating an incrementally increased read count output value; and

an addressing means coupled to receive said read count output value and for addressing said addressable memory in response thereto.

4. The system of claim 3, wherein said cache memory further comprises means for comparing said write count output value and said read count output value, and for generating a signal to said second activation circuit input signal line when said count values are unequal.

5. The system of claim 4, wherein said write counter and said read counter respectively have means for presetting a predetermined maximum count value and means for returning to a zero count value after said maximum count value has been achieved, and wherein said cache memory further comprises means for detecting a signal from the respective said means for incrementally returning to a zero count value to respectively generate a wraparound signal in response thereto.

6. The system of claim 5, wherein said cache memory further comprises means for receiving and for detecting the write counter wraparound signal and means for receiving and for detecting the read counter wraparound signal, and including means for incrementing the count value in said read counter in time coincidence with said write counter whenever a write counter wraparound signal is detected without the corresponding detection of a read counter wraparound signal.

7. The system of claim 6, wherein said cache memory further comprises means connected to said second activation circuit for blocking said second activation signal when said second activation signal appears in time coincidence with said first activation signal.

8. The system of claim 3, wherein said cache memory further comprises an output ready signal line connected to said second activation circuit means for generating a second activation signal, and wherein said FIFO register bank further comprises means for gating data from said cache memory output register into said first register, coupled to said output ready signal line.

9. The system of claim 8, wherein said cache memory further comprises means for comparing said write count output value and said read count output value, and for generating a signal to said second activation circuit input signal line when said count values are unequal.

10. The system of claim 9, wherein said write counter and said read counter respectively have means for presetting a predetermined maximum count value and means for returning to a zero count value after said maximum count value has been achieved, and wherein said cache memory further comprises means for detecting a signal from said means for returning to a zero count value to respectively generate a wraparound signal in response thereto.

11. The system of claim 10, wherein said cache memory further comprises means for receiving and for detecting the write counter wraparound signal and means for receiving and for detecting the read counter wraparound signal, and including means for incrementing the count value in said read counter in time coincidence with said write counter whenever a write counter wraparound signal is detected without the corresponding detection of a read counter wraparound signal.

12. The system of claim 11, wherein said cache memory further comprises means connected to said second activation circuit for blocking said second activation signal when said second activation signal appears in time coincidence with said first activation signal.

13. The system of claim 8, wherein said FIFO register bank further comprises means connected to said FIFO first register for detecting and identifying predetermined signals representative of data stored in said FIFO first register, and means for generating signals representative of an additional data segment responsive to said identified predetermined signals, and means for transferring said signals representative of an additional data segment into the next subsequent register of said plurality of further registers together with the data signals stored in said first register, and means for transferring said signals representative of an additional data segment and said data signals from the next subsequent register to the plurality of further registers and to the output register, sequentially.

14. The system of claim 13, wherein said FIFO register bank further comprises means, connected to one of said registers, for decoding said signals representative of an additional data segment, including means for generating an output decoding signal when predetermined signal combinations are present, and means, responsive to said output decoding signal for enabling and disabling signal transfers between said output register and large store memory.

15. The system of claim 14, wherein said FIFO register bank further comprises presample storage means coupled to said means for decoding said signals representative of an additional data segment and coupled to said means for enabling signal transfers between said output register and said large store memory, said presample storage means having means for enabling further signal transfers between said output register and said large store memory of a predetermined number of sequential signal transfers prior to the transfer of said decoded data segment signals and said associated data signals.

16. The system of claim 15, wherein said FIFO register bank further comprises post sample storage means coupled to said means for decoding said signals representative of an additional data segment and coupled to said means for enabling signal transfers between said output register and said large store memory, said post sample storage means having means for enabling further signal transfers between said output register and said large store memory of a predetermined number of sequential signal transfers after the transfer of said decoded data segment signals and said associated data signals.

17. The system of claim 1, wherein each channel interface circuit further comprises an input line adapted for connection to a digital communication line;

a time-delay signal inversion circuit having an input coupled to said input line and an output;

a logical OR gate and a logical NAND gate, each having two inputs respectively connected in parallel to said input line and said time-delay signal inversion circuit output, each of said OR gate and said NAND gate having an output; and

a further NAND gate having two inputs respectively connected to said OR gate output and said NAND gate output, said further NAND gate having an output.