Semiconductor memory device with shift during write capability

• US 4,773,045 A
• Filed: 10/16/1985
• Issued: 09/20/1988
• Est. Priority Date: 10/16/1984
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Ogawa, Junji
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): Bowler, Alyssa H.
• Application Number:
  US06/788,000
• Time in Patent Office: 1,070 Days
• Field of Search: 365/78, 365/219, 365/238, 365/220
• US Class Current: 365/78
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1036 using data shift registers

Abstract

A semiconductor memory device including a RAM portion and a shift register for enabling parallel transfer of a one word line amount of data of the RAM portion between the RAM portion and the shift register. The shift register is divided into a plurality of shift register portions with serial input data being distributed alternately between the shift register portions by the operation of a multiplexer and serial output data being obtained by picking up data alternately from the shift register portions by the operation of another multiplexer. A transfer gate portion is inserted between the RAM portion and the shift register for carrying out parallel transfer, the transfer gate portion includes a plurality of groups of transfer gates for enabling selective connections of input and output terminals of each of the stages of the shift register portions with either of the adjacent odd numbered bit line and even numbered bit line of the RAM portion. The plurality of transfer gate groups are switched in correspondence with shift clock signals.

Claims

1. A semiconductor memory device, comprising:

a random access memory portion including a plurality of first and second columns;

first and second shift registers, operatively connected to said random access memory portion, for serially inputting into or outputting from said device and enabling parallel transfer, of a one word line amount of data of said random access memory portion, each shift register being devided into a plurality of shift register stages;

first and second transfer gate portions, operatively connected between said random access memory portion and said shift registers, for carrying out parallel transfer therebetween, each of said first and second transfer gate portions including a plurality of groups of direct and shift transfer gates, said shift register stages of said first shift register being connected to said first columns by said direct transfer gates, respectively, and to said second columns via said shift transfer gates, respectively said shift register stages of said second shift register being connected to said second columns by said direct transfer gates, respectively, and to said first columns by said shift transfer gates.

2. A memory device as recited in claim 1, wherein said direct transfer gates comprise transistors connected between stages of said shift register and said columns, and said shift transfer gates comprise transistors connected between the stages of said shift register and said columns.