Oscilloscope trace attribute control system

• US 4,774,438 A
• Filed: 09/05/1986
• Issued: 09/27/1988
• Est. Priority Date: 09/05/1986
• Status: Expired due to Term

• Current Assignee: Tektronix Incorporated (Fortive Corp.)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Rogers, Gregory S., Bennington-Davis, Timothy E.
• Primary Examiner(s): Blum, Theodore M.
• Application Number:
  US06/903,917
• Time in Patent Office: 753 Days
• Field of Search: 315/392, 315/395, 340/740, 340/742
• US Class Current: 315/392
• CPC Class Codes: G01R 13/28 Circuits for simultaneous or sequential presentation of more than one variable

Abstract

In a multiple trace oscilloscope wherein separate traces displayed on a cathode ray tube screen are updated in succession, a random access memory is addressed by the count output of a programmable counter which increments its count each time the oscilloscope finishes updating one trace prior to updating a next trace. Data stored in the random access memory at the storage location addressed by the count is utilized to control attributes of the next trace to be updated by controlling the switching positions of attribute control switches which select the horizontal, vertical and intensity control signals controlling the appearance of each trace.

Claims

1. A trace attribute controller for a multiple trace oscilloscope wherein multiple traces displayed on a screen are successively updated, comprising:

addressable memory means for storing at separate addresses trace attribute control data corresponding to each of multiple input signals and for outputting said trace attribute control data when addressed,

means for generating a succession of addresses for addressing said memory means;

switch means receiving the input signals for providing one of the input signals as an output signal, said one input signal being selected in accordance with trace attribute control data output by said addressable memory means; and

means for controlling an attribute of a trace according to the output signal of said switch means.

2. The trace attribute controller according to claim 1 wherein said addressable memory means comprises a random access memory.

3. The trace attribute controller according to claim 1 wherein said means for generating a succession of addresses comprises a counter.

4. The trace attribute controller according to claim 1 wherein said means for generating a succession of addresses comprises:

means for generating a clock signal indicating a trace is to be updated; and

a counter for maintaining a count of occurrences of said clock signal and for generating said succession of addresses according to said count.

5. The trace attribute controller according to claim 1 wherein said means for generating a succession of addresses comprises:

means for generating a clock signal indicating a trace is to be updated; and

means for maintaining a count of occurrences of said clock signal, said count being reset to a predetermined starting value each time said count reaches a predetermined ending value, and for generating said succession of addresses according to said count.

6. A trace attribute controller for a multiple trace oscilloscope wherein multiple traces displayed on a screen are successively updated, comprising:

means for generating a clock signal each time a trace is to be updated;

adressable memory means for storing at separate addresses trace attribute control data corresponding to each of multiple input signals and for outputting said trace attribute control data when addressed;

means for generating a succession of addresses for addressing said addressable memory means, each address of said succession of addresses being generated in response to said clock signal;

latch means input enabled by said clock signal for storing said trace attribute control data output of said addressable memory means;

switch means receiving the input signals for providing one of the input signals as an output signal, said one input signal being selected in accordance with trace attribute control data stored by said latch means; and

means for controlling an attribute of a trace according to the output signal of said switch means.

7. The trace attribute controller according to claim 6 wherein said addressable memory means comprises a random access memory.

8. The trace attribute controller according to claim 6 wherein said means for generating a succession of addresses comprises a programmable counter for maintaining a count of occurrences of said clock signal, said count being reset to a predetermined starting value each time said count reaches a predetermined ending value, and for generating said succession of addresses according to said count.

9. A trace controller for an instrument that generates multiple traces representing input signals by moving a beam across a screen, the trace controller comprising:

addressable memory means storing at separate addresses trace attribute control data corresponding to separate ones of said multiple traces for outputting trace attribute control data when addressed;

switch means receiving said input signals for providing a selected one of the input signals as an output signal, said one input signal being selected in accordance with trace attribute control data output by said addressable memory means;

means for controlling an attribute of said beam in response to said output signal; and

means for successively addressing said memory means such that said addressable memory means outputs a sequence of trace attribute control data, each data of said sequence corresponding to a separate one of said multiple traces.

10. A trace controller for an instrument having a screen for displaying multiple traces generated by a beam moving across the screen, comprising:

addressable memory means storing at separate addresses trace attribute control data corresponding to separate ones of said multiple traces, for outputting trace attribute control data when addressed;

switch means receiving multiple input signals for providing ones of the input signals as output signals, said ones of said input signals being selected in accordance with trace attribute control data output by said addressable memory means;

means for controlling movement of the beam in accordance with one of said output signals; and

means for successively addressing said memory means such that said addressable memory means outputs a sequence of trace attribute control data, each data of said sequence corresponding to a separate one of said multiple traces.

11. The trace controller in accordance with claim 10 further comprising means for controlling the intensity of said beam in accordance with another of said output signals.

12. A trace controller for an instrument having a screen for displaying multiple traces generated by a beam moving across the screen, comprising:

addressable memory means storing at separate addresses trace attribute control data corresponding to separate ones of the multiple traces for outputting trace attribute control data when addressed;

first switch means receiving a plurality of oscilloscope input signals for providing a selected one of the input signals as a first output signal, said one input signal being selected in accordance with trace attribute control data output by said addressable memory means;

means for controlling vertical movement of the beam across said screen in accordance with the first output signal;

means for generating a plurality of sweep signals;

second switch means receiving said plurality of sweep signals and providing a selected one of the sweep signals as a second output signal, said one sweep signal being selected in accordance with the trace attribute control data output by said addressable memory means;

means for controlling horizontal movement of the beam across said screen in accordance with the second output signal; and

means for successively addressing said memory means such that said addressable memory means outputs a sequence of trace attribute control data, each data of said sequence corresponding to a separate one of said multiple traces.

13. The trace controller in accordance with claim 12 further comprising:

third switch means receiving a plurality of intensity control signals and providing one of the intensity control signals as a third output signal, said one intensity control signal being selected in accordance with the trace attribute control data output by said addressable memory means; and

means for controlling the intensity of the beam in accordance with the third output signal.