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Method and apparatus for DMA window display

  • US 4,777,485 A
  • Filed: 04/05/1988
  • Issued: 10/11/1988
  • Est. Priority Date: 09/13/1985
  • Status: Expired due to Term
First Claim
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1. In a computer display system including:

  • a display capable of displaying a plurality of picture elements (pixels) organized in a plurality of scan lines;

    a frame buffer having a plurality of storage locations, said storage locations having a one to one correspondence with said display pixels; and

    a storage device for storing a plurality of images, each of said images comprising a plurality of data elements;

    an apparatus for controlling the transfer of said image data elements directly from said storage device to a region of said frame buffer corresponding to a predetermined display window, said apparatus comprising;

    (a) a base counter for receiving a predetermined base value and for providing a base address corresponding to a first pixel in one of said scan lines within said predetermined display window;

    (b) a limit counter coupled to said base counter for counting up to a holding limit value and then precluding said base counter from further counting;

    (c) system clock means coupled to said base counter and said limit counter for incrementing said base counter and said limit counter;

    (d) an address output counter coupled to said base counter for receiving said base address and for providing row and column address signals defining a unique address location in said frame buffer;

    (e) a width register for receiving a predetermined width value which defines a display window width;

    (f) a width counter coupled to said width register for counting up to said predetermined width value and then providing a load control signal;

    (g) memory cycle signal generating means coupled to said width counter and said address output counter and responsive to a transfer of image data elements from said storage device for incrementing said width counter and said address output counter in synchronism with said transfer of image data elements from said storage device; and

    (h) wherein said load control signal is coupled to control inputs of said limit counter, said address output counter and said width counter so as to reinitialize said limit counter and said width counter and load said address output counter with said base address upon receipt of said load control signal.

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