Method and apparatus for DMA window display

• US 4,777,485 A
• Filed: 04/05/1988
• Issued: 10/11/1988
• Est. Priority Date: 09/13/1985
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Costello, Peter W.
• Primary Examiner(s): Brigance, Gerald L.
• Assistant Examiner(s): Brier, Jeffery A.
• Application Number:
  US07/177,850
• Time in Patent Office: 189 Days
• Field of Search: 340/721, 340/723, 340/724, 340/725, 340/726, 340/798, 340/799, 340/750
• US Class Current: 345/572
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

The present invention discloses apparatus and methods for direct memory access (DMA) having particular application for use in displaying digital images in an animated form on a CRT display. The present invention includes a DMA controller coupled over a bus to a frame buffer. The frame buffer includes one or more bit maps representative of the display. A block of memory within the frame buffer is mapped onto corresponding picture elements (pixels) on the display. The frame buffer continuously scans the bit map representing the CRT screen such that modifications to data bits within the frame buffer are correspondingly displayed on the screen. A plurality of windows may be displayed on the CRT having varying predefined widths which are appropriately represented within the frame buffer. Digital images stored as sequential "frames" of data in a memory, such as for example a hard disk or RAM memory, may be directly transferred from the memory to the frame buffer for display without the need for central processing unit (CPU) interaction.

Claims

1. In a computer display system including:

a display capable of displaying a plurality of picture elements (pixels) organized in a plurality of scan lines;

a frame buffer having a plurality of storage locations, said storage locations having a one to one correspondence with said display pixels; and

a storage device for storing a plurality of images, each of said images comprising a plurality of data elements;

an apparatus for controlling the transfer of said image data elements directly from said storage device to a region of said frame buffer corresponding to a predetermined display window, said apparatus comprising;

(a) a base counter for receiving a predetermined base value and for providing a base address corresponding to a first pixel in one of said scan lines within said predetermined display window;

(b) a limit counter coupled to said base counter for counting up to a holding limit value and then precluding said base counter from further counting;

(c) system clock means coupled to said base counter and said limit counter for incrementing said base counter and said limit counter;

(d) an address output counter coupled to said base counter for receiving said base address and for providing row and column address signals defining a unique address location in said frame buffer;

(e) a width register for receiving a predetermined width value which defines a display window width;

(f) a width counter coupled to said width register for counting up to said predetermined width value and then providing a load control signal;

(g) memory cycle signal generating means coupled to said width counter and said address output counter and responsive to a transfer of image data elements from said storage device for incrementing said width counter and said address output counter in synchronism with said transfer of image data elements from said storage device; and

(h) wherein said load control signal is coupled to control inputs of said limit counter, said address output counter and said width counter so as to reinitialize said limit counter and said width counter and load said address output counter with said base address upon receipt of said load control signal.