Digital autopilot controller for marine vessels

• US 4,777,602 A
• Filed: 06/26/1986
• Issued: 10/11/1988
• Est. Priority Date: 06/26/1986
• Status: Expired due to Term

• Current Assignee: Sp-Marine Incorporated
• Original Assignee: Sperry Marine, Inc. (Northrop Grumman Corporation)
• Inventors: Wesner, Charles R.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Black, Thomas G.
• Application Number:
  US06/878,556
• Time in Patent Office: 838 Days
• Field of Search: 364/457, 364/443, 364/424, 364/447, 318/588, 114/144 RE, 377/45, 33/1 PT
• US Class Current: 701/224
• CPC Class Codes: G05D 1/0206 specially adapted to water vehicles

Abstract

A heading change unit for a ship'"'"'s autopilot gyrocompass that provides a heading error signal to produce a proportional rudder control signal. An operator enters a heading change which causes an up/down counter to be incremented or decremented in accordance with the heading change order. The counter is also responsive to a step heading input signal. The count is referenced to a zero value and converted to an analog control signal by a digital-to-analog converter. As the ship turns towards the new heading, the changing step heading input will cause the counter to count back to zero. The displayed amount of heading error or ordered heading change is generated by converting the analog heading error signal to a digital encoded format which controls a display. The heading error signal is generated in the form of a parallel twelve bit binary code which represents integer degree changes and 1/6 degree fractional changes.

Claims

1. A heading change controller for a marine vessel having an autopilot for commanding a set course heading and including a gyrocompass, display means for displaying a heading error relative to the set course heading and command means for commanding a differential change in actual course heading comprising:

(a) level shift means coupled to receive step data signals from said gyrocompass at a first predetermined voltage level for providing output step data signals at a second predetermined voltage level;

(b) first logic means coupled to said level shift means for converting said output step data signals to first binary signals and responsive to signals from said command means for providing pulse signals representative of course deviations;

(c) second logic means coupled to said first logic means to receive said first binary signals for generating second binary signals representative of magnitude and direction of fractional degree deviations from a set course heading;

(d) means coupled to said first logic means and responsive to said pulse signals for generating third binary signals representative of magnitude and direction of integer degree deviations from said set course heading;

(e) DAC means coupled to receive said second binary signals from said second logic means and said third binary signals from said integer degree deviation means for converting said second and third binary signals to analog signals representative of course deviations; and

(f) means for coupling said analog signals to said display means to provide a visual digital readout of command direction and heading error in integer degrees and fractions of a degree.

2. Apparatus as in the claim 1 further comprising first clock generation means responsive to said step data signals for providing clock signals to said first logic means synchronized with said step data signals, said synchronized clocked signals utilized by said first logic means to provide said output step data signals without ripple thereon.

3. Apparatus as in claim 2 further comprising second clock generation means responsive to said command means for generating signals coupled to and utilized by said first logic means for providing said pulse signals to said third binary signal generating means.

4. Apparatus as in claim 3 further comprising inverter means coupled between said first clock generation means and said second logic means for providing timing signals to said second logic means.