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Process of forming input/output wiring areas for semiconductor integrated circuit

  • US 4,778,771 A
  • Filed: 02/12/1986
  • Issued: 10/18/1988
  • Est. Priority Date: 02/14/1985
  • Status: Expired due to Term
First Claim
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1. A process of forming input/output wiring areas on a semiconductor integrated circuit, the process comprising the steps of(a) preparing a semiconductor wafer;

  • (b) forming a plurality of device-forming areas on the wafer, each of the device-forming areas including a plurality of functional devices, the device-forming areas being arranged in a matrix form on the wafer;

    (c) forming interconnection wiring areas on said device-forming areas, respectively, each of said device-forming areas and the interconnection wiring area on each device-forming area providing an incomplete integrated circuit portion;

    (d) inspecting each of the incomplete integrated circuit portions for defects in functions and capabilities of the functional devices included in each device-forming area, determining that said inspected portions are acceptable or nonacceptable; and

    (e) forming input/output terminal areas for only those of said incomplete integrated circuit portions which have been determined to be acceptable as a result of the inspection step, each of said input/output terminal areas being formed in part substantially throughout the area of each of the incomplete integrated circuit portions determined in step (d) to be acceptable and in part in the areas of the incomplete integrated circuit portions which have been determined in step (d) to have said defects and which are located contiguously to each of said incomplete integrated circuit portions determined in step (d) to be acceptable, each of said input/output terminal areas comprising input/output terminal pad regions located within said areas of the incomplete integrated circuit portions which have been determined in step (d) to have said defects, wherein the input/output termional pad regions for the incomplete integrated circuit portions determined in step (d) to be acceptable are retained in situ within the respective input/output terminal areas.

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