Process of forming input/output wiring areas for semiconductor integrated circuit

• US 4,778,771 A
• Filed: 02/12/1986
• Issued: 10/18/1988
• Est. Priority Date: 02/14/1985
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Hiki, Yoshimasa
• Primary Examiner(s): Chaudhuri, Olik
• Application Number:
  US06/829,424
• Time in Patent Office: 979 Days
• Field of Search: 437/8, 437/51, 437/204, 324/158 T
• US Class Current: 438/6
• CPC Class Codes: G01R 1/07342 the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A process of fabricating a semiconductor integrated circuit wherein a plurality of device-forming areas are formed on a semiconductor wafer, whereupon, interconnection wiring patterns are formed on the device-forming areas, respectively, so that each of the device-forming areas and the interconnection wiring pattern on the particular device-forming area form an incomplete integrated circuit portion. Each of the incomplete integrated circuit portions is then inspected for defects in functions and capabilities thereof, whereupon input/output terminal wiring patterns are formed only for those of the incomplete integrated circuit portions which have been determined to be acceptable as a result of the inspection step.

Claims

1. A process of forming input/output wiring areas on a semiconductor integrated circuit, the process comprising the steps of

(a) preparing a semiconductor wafer;

(b) forming a plurality of device-forming areas on the wafer, each of the device-forming areas including a plurality of functional devices, the device-forming areas being arranged in a matrix form on the wafer;

(c) forming interconnection wiring areas on said device-forming areas, respectively, each of said device-forming areas and the interconnection wiring area on each device-forming area providing an incomplete integrated circuit portion;

(d) inspecting each of the incomplete integrated circuit portions for defects in functions and capabilities of the functional devices included in each device-forming area, determining that said inspected portions are acceptable or nonacceptable; and

(e) forming input/output terminal areas for only those of said incomplete integrated circuit portions which have been determined to be acceptable as a result of the inspection step, each of said input/output terminal areas being formed in part substantially throughout the area of each of the incomplete integrated circuit portions determined in step (d) to be acceptable and in part in the areas of the incomplete integrated circuit portions which have been determined in step (d) to have said defects and which are located contiguously to each of said incomplete integrated circuit portions determined in step (d) to be acceptable, each of said input/output terminal areas comprising input/output terminal pad regions located within said areas of the incomplete integrated circuit portions which have been determined in step (d) to have said defects, wherein the input/output termional pad regions for the incomplete integrated circuit portions determined in step (d) to be acceptable are retained in situ within the respective input/output terminal areas.

2. A process as set forth in claim 1, in which each of said input/output terminal areas comprises conductor regions which include interconnection wiring areas electrically connected to said device-forming areas and to said input/output terminal pad regions.

3. A process as set forth in claim 2, in which said input/output terminal pad regions include testing pad regions which are located within the area of each of the incomplete integrated circuit portions determined in step (d) to be acceptable.

4. A process of forming input/output wiring areas on a semiconductor integrated circuit, the process comprising the steps of

(a) preparing a semiconductor wafer;

(b) forming a plurality of device-forming areas on the wafer, each of the device-forming areas including a plurality of functional devices, the device-forming areas being arranged in a matrix form on the wafer;

(c) forming interconnection wiring areas on said device-forming areas, respectively, each of said device-forming areas and the interconnection wiring area on each device-forming area providing an incomplete integrated circuit portion;

(d) inspecting each of the incomplete integrated circuit portions for defects in functions and capabilities of the functional devices included in each device-forming area, determining that said inspected portions are acceptable or nonacceptable; and

(e) forming input/output terminal areas for only those of said incomplete integrated circuit portions which have been determined to be acceptable as a result of the inspection step, in which each of said input/output terminal areas is formed in part substantially throughout the area of each of the incomplete integrated circuit portions determined in step (d) to be acceptable and in part in the areas of the incomplete integrated circuit portions which have been determined in step (d) to have said defects and be non-acceptable and which are located contiguously to each of said incomplete integrated circuit portions determined in step (d) to be acceptable, wherein each of said input/output terminal areas comprises input/output terminal pad regions located within said areas of the incomplete integrated circuit portions which have been determined in step (d) to have said defects, and interconnection wiring areas electrically connected to said device-forming areas and to said input/output terminal pad regions, said input/output terminal pad regions including testing pad regions which are distributed substantially throughout each of said device-forming areas and which are located within the area of each of the incomplete integrated circuit portions determined in step (d) to be acceptable, wherein the input/output terminal pad regions for the incomplete integrated circuit portions determined in step (d) to be acceptable are retained in situ within the respective input/output terminal areas.

5. A process as set forth in claim 4, further comprising the step of forming in at least part of each of said input/output terminal areas an insulator covering a portion of each of said testing pad regions and a plurality of input/output terminal wiring regions overlying said insulator layer and electrically connected to the testing pad regions located within the areas of the imcomplete integrated circuit portions which have been determined in step (d) to be acceptable.