Bus arbitration controller

• US 4,779,089 A
• Filed: 02/16/1988
• Issued: 10/18/1988
• Est. Priority Date: 11/27/1985
• Status: Expired due to Fees

• Current Assignee: F & S Corporation of Columbus Georgia
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Theus, John G.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Smith, Ralph E.
• Application Number:
  US07/158,101
• Time in Patent Office: 245 Days
• Field of Search: 340/825.5, 340/825.51, 340/825.05, 340/825.83, 370/85, 370/93, 364/200
• US Class Current: 710/244
• CPC Class Codes: G06F 13/374 using a self-select method with individual priority code comparator

Abstract

A bus arbitration controller controls access of a plurality of asynchronous potential master devices to a unitary interconnecting bus by forming a distributed state machine of arbitration logic units in each of the potential master devices. Each arbitration logic unit receives control signals by way of the unitary bus which are common to all the devices, each control signal being the logical OR of the corresponding signals from all other devices. The control signals include a device address/priority number and a synchronization signal set. The arbitration logic includes a priority resolver which awards bus access to a device having the highest address/priority number, and control logic which receives the common synchronization signal set and synchronizes the operation of the device in which the arbitration logic resides with all other devices contending for the unitary bus. The control logic and the priority resolver are programmable array logic circuits.

Claims

1. In a computer system havig a unitary bus and at least two asynchronous devices each coupled through a respective bus transceiver unit to the unitary bus, and an arbitration controller distributed in the asynchronous devices resolving contention for access to the unitary bus by the asynchronous devices, the unitary bus having a plurality of control signal lines including a priority arbitration signal set AN0*-AN5*, an arbitration condition signal AC*, and a synchronization signal set AP*, AQ* and AR*, each of the control signal lines being common to each of the asynchronous devices and coupled to each said asynchronous device by wired-OR logic through the respective bus transceiver units, the synchronization control signal set being coupled through integrator and threshold circuit means for preventing wired-OR glitches, wherein the improvement comprises:

control logic means in each of one of the asynchronous devices for synchronizing the operation of the asynchronous devices by way of the unitary bus, the control logic means receiving control signals GREQ, BRST, GMT, HIGHP and LOCK from the one asynchronous device, the control signals AC*, AP*, AQ* and AR* from the unitary bus respectively as control signals AC, APF, AQF and ARF, and providing control signals GMK, HOVR, FL and CM to the one asynchronous device, the control logic means providing an arbitration condition signal C and a synchronization control signal set P, Q and R each coupled respectively through the bus transceiver unit to the control signal lines AC*, AP*, AQ* and AR* of the unitary bus;

means in each one of the asynchronous devices coupled to the control logic means for resolving priority among the plurality of devices for access to the unitary bus, the priority resolving means receiving priority signals GA0-GA4 and the HIGHP control signal from the one asynchronous device, the control signals AN0*-AN5* from the unitary bus respectively as control signals AA0-AA5, and providing a control signal ZERO to the one asynchronous device, the priority resolving means providing a priority arbitration signal set BO0-BO5 coupled respectively through the bus transceiver unit to the control signal lines AN0*-AN5* of the unitary bus;

means in each one of the asynchronous devices receiving a first timing signal from the one asynchronous device and a second timing signal ENCT from the control logic means and providing a timing signal RP for timing the operation of the control logic means;

the control logic means comprising combinatorial logic ##EQU3##

2. The computer system of claim 1, wherein said priority resolving means comprises a programmable array logic circuit.

3. The computer system of claim 1, wherein said control logic means comprises a programmable array logic circuit.