Selective guest system purge control

• US 4,779,188 A
• Filed: 10/19/1987
• Issued: 10/18/1988
• Est. Priority Date: 12/14/1983
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tallman, Peter H., Curlee, Thomas O. III, Hough, Roger E., Gum, Peter H.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Lynt, Christopher H.
• Application Number:
  US07/110,620
• Time in Patent Office: 365 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 718/1
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2009/45579 I/O management, e.g. providing access to device drivers or storage
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 2212/682 Multiprocessor TLB consistency
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

The embodiments enable address translations for a virtual machine in the TLB (translation lookaside buffer) of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are defined which determine when guest TLB entries must be invalidated. These conditions require invalidation of guest TLB entries only within and on entry to interpretive execution. A single invalidation of guest TLB entries on entry to interpretive execution is required for any number of conditions recognized while a CPU is not in interpretive execution state. For a guest in a virtual multi-processor (MP) machine, an interlock is provided to allow the use of guest virtual addresses by host instruction simulation and the need for guest TLB invalidation is broadcast to all other real CPUs in a real MP system so that all guest TLBs on all real CPUs can be invalidated to maintain integrity. No broadcast or interlock is needed for a guest in a virtual uni-processor (UP) machine.

Claims

1. A method for handling address translations made by a virtual system (guest) emulated on a real uniprocessor (UP) data processing system having a real CPU and a real main storage, guest address translations being put into guest identified entries (guest TLB entries) in a translation lookaside buffer (TLB) of the real CPU while the CPU is in emulation state, the method comprising:

providing a state description control block (SD) in the real main storage for defining each virtual CPU in the data processing system,

defining a unique SD identifier (SDI) for each SD in the system,

also providing at least one SD identifier field (SDAR) for the real CPU to contain an identifier (SDI) to a previous SD used by this CPU,

setting the SDAR for the real CPU to the SD identifier (SDI) of the SD for each guest dispatched on the real CPU,

comparing the content of a previous SDI entered in the SDAR of the real CPU with the SDI of a next guest on the real CPU,

not invalidating any guest TLB entry in the CPU if the comparing operation finds the SDI of the next guest is equal to the SDI in the SDAR for the real CPU, so that existing guest TLB entries are allowed to be used by the guest for a guest program, but invalidating the existing guest TLB entries if inequality is found by the comparing operation.

26. A method as defined in claims 1 or 2, further comprising:

assigning a main storage address (SDA) of each SD in the system as the SDI for each SD.

2. A method for handling address translations made by a virtual system (guest) emulated on a multiprocessing (MP) real system having a real main storage and a plurality of real CPUs, guest address translations being put into guest identified entries (guest entries) in a translation lookaside buffer (TLB) of any real CPU in the MP real system while the CPU is in emulation state, having a plurality of state descriptor control blocks (SDs) in main storage and each SD representing a virtual CPU and having an SD identifier (SDI) for locating the SD, the MP real system containing one or more virtual systems which may include one or more virtual UP systems (UP guests) and one or more virtual MP systems (MP guests), each UP guest having an associated SD, and each MP guest having a plurality of associated SDs, each SD in main storage being assignable to a virtual MP system or to a virtual UP system, and a CPU identifier (CPU ID) being provided for each real CPU in the MP real system, the method comprising:

locating each SD in the real main storage,

providing in each SD a last CPU ID field for identifying the last real CPU to use the SD,

also providing an SDI register for each real CPU, setting the SDI register of a real CPU to a SDI of a virtual CPU being dispatched upon the real CPU,

comparing a previous SDI entered into the SDI register for a real CPU with the SDI of a next guest being dispatched on the real CPU, the next guest being dispatched then becomes the guest on the real CPU,

also comparing the content in the last CPU ID field in the SD for the guest being dispatched with the CPU ID for the real CPU upon which the guest is being dispatched,

not invalidating any guest TLB entry in the real CPU if the comparing operations find the SDI of the guest being dispatched is equal to the previous SDI in the SDI register, and if the last CPU ID field in the SD of the guest compares equal to the CPU ID of the real CPU, so that the existing guest TLB entries in the CPU are allowed to be used by the guest for a guest program, and

invalidating guest TLB entries for the guest being dispatched in the real CPU while in emulation mode if the comparing operations find the last CPU ID field in the SD of the guest being dispatched is not equal to the CPU ID of the real CPU, or if the previous SDI in the SDI register compares unequal with the SDI of the guest being dispatched.

3. A method as defined in claim 2, further comprising:

providing a purge guest translation (PRGT) flag for each real CPU in the MP real system, and providing a host control program having at least one host page table in main storage,

setting on the PRGT flag for each real CPU in the system when the host is invalidating a host page table entry.

4. A method as defined in claim 3, further comprising:

testing the PRGT flag for a real CPU in the MP real system on which a next guest is to be dispatched,

invalidating all existing guest TLB entries in the real CPU if the testing of the PRGT flag finds it on for the real CPU,

but not invalidating any existing guest TLB entries in the real CPU if the testing of the PRGT flag finds it off for the real CPU, so that the existing guest TLB entries of the real CPU can be used by the guest.

5. A method as defined in claim 4 when conditions exist for invalidating all existing guest TLB entries, further comprising:

storing the CPU ID for the real CPU in the last CPU ID field in the SD of a guest being dispatched by the host,

setting the SDI registers for the CPU with the SDI of the SD of the guest being dispatched,

resetting off the PRGT field for the CPU,

putting the CPU in emulation state and executing a guest program on the CPU.

6. A method as defined in claim 3, further comprising:

executing an invalidate page table entry (IPTE) instruction by the host on a real CPU to set on the PRGT flag for each real CPU.

7. A method as defined in claim 6, further comprising:

an invalidate page table entry (IPTE) instruction being executed by the host on a real CPU to set on the PRGT flag for each real CPU,

invalidating a page table entry specified by the IPTE instruction and any existing TLB entry used by the host (host TLB entry) in the TLB of the real CPU located by operand(s) of the IPTE instruction,

broadcasting by the real CPU to other real CPUs in the MP real system of an operand representation for the IPTE instruction for the host,

completing processing for the IPTE instruction when all of the other real CPUs have indicated their response.

8. A method as defined in claim 7, further comprising:

providing a guest MP control field (GMP) in real main storage for each virtual MP system (MP guest) which may execute in a real MP system,

representing a virtual MP system with a plurality of SDs in a real main storage, each SD representing a virtual CPU in the virtual MP system and each SD of the virtual MP system defining a common virtual main storage for the virtual MP system,

further providing a GMP address field (GMPA in each SD, each SD of a virtual MP system containing an address to the same GMP, and the content of the GMPA being changeable to allow for reassignment of each SD.

9. A method as defined in claim 8, further comprising:

having an IPTE intercept flag field in each SD, the IPTE intercept flag being set off in an SD when a guest control program of any virtual MP system is to execute a guest IPTE instruction for the virtual CPU represented by the SD.

10. A method as defined in claim 9, further comprising:

testing the state of the GMPA in the SD for a guest to determine if the SD is assigned to a virtual MP system or to a virtual UP system,

executing an IPTE instruction on a real CPU for a virtual CPU if the test of the GMPA finds a zero content indicating the SD is assigned to a virtual UP system (UP guest),

but executing an IPTE instruction on a real CPU for a virtual MP system (MP guest) if the test of the GMPA finds a non-zero content indicating the SD is assigned to a virtual MP system (MP guest).

11. A method as defined in claim 10, further comprising:

issuing virtual UP system being emulated on a real CPU of a real MP system,

invalidating a guest page table entry specified by the guest IPTE instruction being issued,

also invalidating any existing guest TLB entry for the virtual UP system on this real CPU located by operand(s) of the issued IPTE instruction to complete the execution for the guest IPTE instruction,

broadcasting an IPTE signal to each other real CPU in the real MP system if the GMPA in the SD is not zero, but not broadcasting any IPTE signals to any other real CPU if the GMPA in the SD is zero,

whereby the execution is completed for a UP guest issuing an IPTE instruction in a MP system.

12. A method as defined in claim 10, further comprising:

issuing a guest IPTE instruction by a guest program for a virtual MP system being emulated in a real MP system,

setting to an on state a GMP addressed by the GMPA in the SD for a virtual CPU in the virtual MP system issuing the IPTE instruction,

invalidating a guest page table entry specified by the issued guest IPTE instruction,

also invalidating any guest TLB entry for the guest program located by operand(s) of the issued IPTE instruction in the real CPU on which the guest program is being executed for the virtual MP system,

broadcasting by the real CPU executing the guest program of an address for the issued IPTE instruction to each other real CPU in the real MP system which may be emulating a virtual CPU represented by any SD of the same virtual MP system as the broadcasting CPU,

resetting the GMP to an off state after all real CPUs have responded to the IPTE broadcasting to complete the processing of an IPTE instruction issued by the virtual MP system.

13. A method as defined in claim 7, each other real CPU in the real MP system receiving the broadcasting operation, further comprising:

invalidating in each other real CPU any host TLB entry located by the broadcast IPTE operation representation for invalidating a host page frame,

purging a TLB entry used by a virtual CPU (guest TLB entry) in the real CPU which addresses the host page frame being invalidated if the real CPU is in emulation state, but not purging any guest TLB entry in the real CPU if the CPU is not in emulation state,

responding by the other real CPU to the broadcasting CPU when the other real CPU completes processing for the broadcast IPTE instruction.

14. A method as defined in claim 13, further comprising:

trapping the IPTE broadcast signals in each other real CPU receiving an IPTE broadcast,

sensing the completion of a current instruction being executed in each other real CPU receiving the IPTE broadcast signals,

detecting in each other real CPU any trapped IPTE broadcast signals to determine the IPTE operand representation,

invalidating any TLB entry located by the broadcast IPTE operand representation in the other real CPU receiving the IPTE broadcast signals.

15. A method as defined in claim 14, further comprising:

detecting in each real CPU receiving an IPTE broadcast if the receiving CPU is in emulation state,

purging all guest TLB entries which address a host page being invalidated by a TLB entry being invalidated in the receiving CPU if emulation state is detected,

signalling by the receiving CPU to the broadcasting CPU that requested IPTE processing is complete in this receiving CPU,

executing a next instruction in the receiving CPU.

16. A method as defined in claim 2 when conditions exist for invalidating all existing guest TLB entries, further comprising:

storing the CPU ID for a real CPU in the last CPU ID of an SD being addressed by a host control program,

setting the SDI register for the real CPU with the SDI of an SD being identified by the host program,

putting the real CPU in emulation state and executing a guest program on the real CPU.

17. A method as defined in claim 16, further comprising:

an invalidate page table entry (IPTE) instruction being executed by a host program on a real CPU to invalidate a host page frame in main storage,

invalidating a page table entry specified by the IPTE instruction and any corresponding host TLB entry in a TLB in a real CPU located by operand(s) of the IPTE instruction,

also invalidating all affected guest TLB entries in the real CPU,

broadcasting by the real CPU to other real CPUs in the MP real system of an operand representation for the IPTE instruction,

completing the operation of the host IPTE instruction for the host when responses to the broadcasting operation have been received from the other real CPUs.

18. A method as defined in claim 16, further comprising:

providing a guest MP control field (GMP) in real main storage for each virtual MP system (MP guest) which may execute in the MP real system,

further providing a GMP address field (GMPA) in each SD, each SD of a virtual MP system containing an address to the same GMP,

testing the state of the GMPA in an SD for a zero or non-zero content to determine if the SD is in a virtual UP system or in a virtual MP system, the broadcasting operation for an IPTE instruction being required for a virtual MP system,

executing an IPTE instruction for a on a real CPU for a virtual UP system without a broadcasting operation if the test of the GMPA finds a zero content,

but executing an IPTE instruction for a virtual MP system if the test of the GMPA finds a non-zero content.

19. A method as defined in claim 18, further comprising:

having an IPTE intercept flag field in each SD, the IPTE intercept flag being set off in the SD when a guest program is to execute a guest IPTE instruction.

20. A method as defined in claim 19, further comprising:

issuing a guest IPTE instruction by a guest progrm dispatched for a virtual UP system being emulated on a real CPU of the MP real system,

invalidating a guest page table entry specified by the guest IPTE instruction being issued,

also invalidating any other guest TLB entry on the same real CPU located by operand(s) of the issued IPTE instruction,

not broadcasting any IPTE signals to any other real CPU in the MP real system,

whereby execution is completed for an IPTE instruction issued by a virtual UP system in a real MP system.

21. A method as defined in claim 19, further comprising:

issuing a guest IPTE instruction by a guest program of a virtual MP system being emulated by plural SDs in one or more real CPUs in the MP real system,

setting to an on state a GMP addressed by the GMPA in any SD associated with the guest program issuing the IPTE instruction,

invalidating a guest page table entry specified by the issued guest IPTE instruction,

also invalidating any guest TLB entry located by operand(s) of the issued IPTE instruction in the real CPU on which the guest program is being executed for the virtual MP system,

broadcasting by the real CPU executing the guest program of an address for the issued IPTE instruction to each other real CPU being used by the virtual MP system in the real MP system,

resetting the GMP to an off state after each real CPU in the virtual MP system has responded to the IPTE broadcasting operation.

22. A method as defined in claim 21, further comprising:

trapping IPTE broadcast signals in each real CPU receiving an IPTE broadcast,

sensing the completion of a current instruction being executed in each real CPU receiving IPTE broadcast signals,

detecting by each real CPU having any trapped IPTE broadcast signals to determine the IPTE operand representation and if the broadcast was for the host or for a virtual MP guest, invalidating only the guest TLB entries for a particular guest identified by the IPTE broadcast signals to each receiving real CPU,

but invalidating all existing guest TLB entries in the receiving real CPU if the host is identified as sending the trapped IPTE broadcast signals,

also invalidating any host TLB entry from the TLB in the receiving real CPU if the host is identified as sending the trapped IPTE broadcast signals,

signalling by each receiving real CPU to the broadcasting CPU that IPTE processing for the broadcast is complete in the signalling real CPU,

executing a next instruction by the signalling real CPU.

23. A method as defined in claim 21, during which another real CPU in the real MP system can be used by a host program which is simulating an instruction intercepted from a guest program on a virtual CPU of a virtual MP system in the real MP system, the host program further comprising:

requesting a fetch or store request by the host program for the instruction being simulated,

testing the state of a GMP accessed with a GMPA in a SD for the virtual CPU for which the instruction is being simulated by the host,

setting the GMP to an on state when the test finds the GMP is in an off state, the on state of the GMP indicating to other potential users of the storage of the virtual MP system that its storage is not accessible to another request while the GMP is set to an on state,

performing the fetch or store request in the storage of the virtual MP system while the GMP is in the on state,

setting the GMP to off state when operations for the fetch or store request are completed,

continuing with a next host program operation.

24. A method as defined in claim 23, further comprising:

causing the invalidation of guest TLB entries for a current guest on all real CPUs in a real MP by setting a predetermined value for a CPUID in the SD for the same guest.

25. A method as defined in claim 24, further comprising:

assigning an all one'"'"'s value as the predetermined value.