Interface device for controlling command and data transfer between a host computer and a disk controller

• US 4,779,196 A
• Filed: 02/21/1986
• Issued: 10/18/1988
• Est. Priority Date: 03/07/1985
• Status: Expired due to Fees

• Current Assignee: Alcatel SA (Nokia Corporation)
• Original Assignee: Alcatel NV (Nokia Corporation)
• Inventors: Manga, Salih
• Primary Examiner(s): Zache, Raulfe B.
• Assistant Examiner(s): Coleman, Eric
• Application Number:
  US06/831,695
• Time in Patent Office: 970 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/200
• US Class Current: 710/310
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device

Abstract

To control the transfer of commands and data, an interface device is connected to a host computer by a first data bus, an address bus, and first control-signal lines, and to a disk controller by a second data bus and second, third, and fourth control-signal lines. The interface device includes a first internal bus and a second internal bus interconnected via a first controllable buffer and a second controllable buffer, with the first data bus connected to the second internal bus through a third controllable buffer, and the second data bus to the first internal bus through a fourth controllable buffer. An interface controller is connected to the address bus and to the first, second, and third control-signal lines and, via internal control-signal lines, to the controllable buffers. The third and fourth control-signal lines and an error-signal line are connected to the second internal bus via a fifth controllable buffer.

Claims

1. Interface device for controlling the command and data transfer between a host computer and a disk controller, the host computer comprising a first data bus, an address bus, and first control-signal lines, and the disk controller comprising a second data bus and second, third, and fourth control-signal lines, characterized in that the interface device contains a first internal bus and a second internal bus which are interconnected via a first controlled buffer for a first direction of transfer and via a second controlled buffer for a second direction of transfer, that a first check-bit generator and a second check-bit generator are coupled to the first internal bus, that the first data bus is connected to the second internal bus via a third controlled buffer, that the second data bus is connected to the first internal bus via a fourth controlled buffer, that the address bus and the first, second, and third control-signal lines are connected to an interface controller, that the host computer is connected with the interface controller via the address bus and the first control-signal lines, that the disk controller is connected with the interface controller via the second and third control-signal lines, that to transfer a status word indicating the status of the disk controller the third and fourth control-signal lines from the disk controller are connected to the second internal bus via a fifth controlled buffer and an error-signal line is connected to an output of the second check-bit generator and to the second internal bus via the fifth controlled buffer, that the first and second check-bit generators are connected to a sixth controlled buffer linked to the disk controller by a check-bit line, and that the interface controller is connected to the controlled buffers by internal control-signal lines.

2. An interface device as claimed in claim 1, characterized in that the first control-signal lines comprise a write-enable-signal line, a read-enable-signal line, a first select-signal line, an interrupt-signal line, a first request-signal line, and a first reset-signal line.

3. An interface device as claimed in claim 1, characterized in that the second control-signal lines consist of a second select-signal line, a second reset-signal line, and an acknowledge-signal line, that the third control-signal lines consist of a busy-signal line and a command-acknowledge-signal line, and that the fourth control-signal lines contain an input/output signal line, a command/data signal line, and a second request signal line.

4. An interface device as claimed in claim 1, characterized in that a seventh controllable buffer is connected to a fixed potential and to the least significant bit line of the first internal bus and is so controlled over an additional internal-control-signal line that the least significant bit line is at a logic level representing the fixed potential.

5. An interface device as claimed in claim 1, characterized in that the interface controller comprises a command decoder, a select logic, an interrupt and DMA controller, and a control logic which are interconnected by command lines.

6. An interface device as claimed in claim 2, characterized in that the address bus and the first select-signal line are connected to the command decoder, that according to the addresses transferred from the host computer over the address bus into the command decoder, commands decoded by the command decoder are transferred out over a first command line, a second command line, a third command line, a fourth command line, and a fifth command line to a select logic, over a sixth command line both to the select logic and to a control logic, and over a seventh command line and to an eighth command line both to the select logic and to an interrupt and DMA controller, the sixth command line and the seventh command line also forming two of the internal control-signal lines and being connected to the fifth controller buffer and the second controllable buffer, respectively.

7. An interface device as claimed in claim 5, characterized in that the address bus and the first select-signal line are connected to the command decoder, that according to the addresses transferred from the host computer over the address bus into the command decoder, decoded commands are transferred out over a first command line, a second command line, a third command line, a fourth command line, and a fifth command line to the select logic, over a sixth command line both to the select logic and to the control logic, and over a seventh command line and an eighth command line both to the select logic and to the interrupt and DMA controller, the sixth command line and the seventh command line also forming two of the internal control-signal lines and being connected to the fifth controllable buffer and the second controllable buffer, respectively.

8. An interface device as claimed in claim 3, characterized in that a select logic is connected to a first reset-signal line, to a second reset-signal line, and to the second select-signal line, that an output of a select logic is coupled back to an input of the select logic via a ninth command line, and that a tenth command line connects the select logic both to a control logic and-as an additional internal control - signal line - to a seventh controlled buffer.

9. An interface device as claimed in claim 4, characterized in that a select logic is connected to a first reset-signal line, to a second reset-signal line, and to a second select-signal line, that an output of the select logic is coupled back to an input of the select logic via a ninth command line, and that a tenth command line connects the select logic both to the control logic and--as an additional internal control-signal line--to the seventh controlled buffer.

10. An interface device as claimed in claim 6, characterized in that the select logic is connected to a first reset-signal line, to a second reset-signal line, and to the second select-signal line, that an output of the select logic is coupled back to an input of the select logic via a ninth command line, and that a tenth command line connects the select logic both to the control logic and - as an additional internal control-signal line - to a seventh controlled buffer.

11. An interface device as claimed in claim 7, characterized in that the interrupt and DMA controller is connected to a first request-signal line, a interrupt signal line, a first reset-signal line, a second request-signal line, a input/output signal line, a command/data signal line, and the error-signal line.

12. An interface device as claimed in claim 8, characterized in that an output of the control logic is coupled back to an input of the control logic via an eleventh command line, that the control logic is connected to an interrupt and DMA controller by a twelfth command line and a thirteenth command line, that a write-enable-signal line and a read-enable-signal line are connected to a control logic, and that the eleventh command line and first, second, third, fourth, and fifth logic-signal lines connected to the outputs of the control logic form six of the internal control-signal lines.

13. An interface device as claimed in claim 3, characterized in that the first reset-signal line, the first command line, and an internal reset circuit are connected via a logic gate to the select logic such that respective reset signals on the first resetsignal line, on the first command line and from the internal reset circuit, are applied to the select logic one at a time.

14. An interface device as claimed in claim 5, characterized in that the first reset-signal line, the first command line, and an internal reset circuit are connected via a logic gate to the select logic such that respective reset signals on the first resetsignal line, on the first command line and from the internal reset circuit, are applied to the select logic one at a time.

15. An interface device as claimed in claim 6, characterized in that the first reset-signal line, the first command line, and an internal reset circuit are connected via a logic gate to the select logic such that respective reset signals on the first resetsignal line, on the first command line and from the internal reset circuit, are applied to the select logic one at a time.