Antenna with integral tuning element

• US 4,780,724 A
• Filed: 04/18/1986
• Issued: 10/25/1988
• Est. Priority Date: 04/18/1986
• Status: Expired due to Fees

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: General Electric Company
• Inventors: Sharma, Arvind K., Stabile, Paul J.
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): LE, HOANGANH T
• Application Number:
  US06/853,739
• Time in Patent Office: 921 Days
• Field of Search: 343/700 MS, 343/745, 333/104
• US Class Current: 343/700.0MS
• CPC Class Codes: H01Q 9/0442 with particular tuning means

Abstract

A patch antenna, which may be one element of an antenna array, is formed on one broad surface of a semiconductor plate. A ground plane is formed on the second broad surface. This semiconductor is doped in regions near a periphery of the patch to define a semiconductor PN junction have electrode contacts to the patch and to the ground plane. The junction has capacitance which tunes the patch antenna. The characteristics of the junction are controlled by bias to selectively tune the patch antenna. The bias is a direct voltage in one embodiment of the invention. In another embodiment, the junction work function itself provides a bias which is controlled by temperature control of the diode.

Claims

1. An antenna arrangement, comprising:

a planar substantially intrinsic semiconductor substrate including first and second broad sides;

a first planar conductive element attached to said first broad side of said substrate;

a second planar conductive element attached to said second broad side of said substrate; and

at least one semiconductor P-N diode having associated capacitance and including first and second adjacent electrodes of opposite conductivity type formed within said substrate, said first electrode being galvanically connected to said first planar conductive element, and said second electrode being glavanically connected to said second planar conductive element for electrically connecting said diode between said first and secondf planar conductive elements.

2. An arrangement according to claim 1 wherein said first planar conductive element is a rectangular patch and said second planar conductive element is a groound plane.

3. An arrangement according to claim 1 further comprising biasing means coupled to said diode for controlling said capacitance.

4. An arrangement according to claim 3 wherein said biasing means comprises a source of direct voltage.

5. An arrangement according to claim 1 further comprising an elongated planar conductive element attached to said first broad side of said substrate, one end of said elongated planar conductive element being electrically continuous with said first planar conductive element, said elongated planar conductive element coacting with said second planar conductive element to define a transmission line.

6. An arrangement according to claim 5 further comprising biasing means coupled to said diode for controlling said capacitance.

7. An arrangement according to claim 6 wherein said biasing means comprises:

a source of direct voltage; and

low pass filter means coupled to said source of direct voltage and to a point along said elongated planar conductive element for coupling said direct voltage from said source of direct voltage to said diode by way of said elongated planar conductive element and first planar conductive elements, and for preventing significant amounts of signal from leaking from said elongated planar conductive element to said source of direct voltage.

8. An antenna array, comprising:

a planar substantially intrinsic semiconductor substrate including first and second broad sides;

at least first and second separated planar conductive elements attached to said first broad side of said substrate;

;

11. An array according to claim 8 wherein said first and second planar conductive elements are rectangular patches, and said third planar conductive element is a ground plane.

12. An array according to claim 8 wherein said first semiconductor diode comprises:

a doped surface portion near the surface of said first broad side of said planar substantially intrinsic semiconductor substrate, said doped surface portion including a first region which is heavily doped with one of n and p impurities, said first region lying under and being in contact with said first planar conductive element for forming an ohmic contact between said first planar conductive element and said doped surface portion;

a conductive via hole extending between said first and second broad sides of said planar substantially intrinsic semiconductor substrate in a second region of said doped surface portion, said second region being heavily doped with the other of said n and p impurities for forming an ohmic contact between said doped surface portion and said via hole, thereby creating said semiconductor diode as a transverse diode in said doped surface portion.

13. An array according to claim 8, comprising:

first and second elongated planar conductive elements attached to said first broad side of said substrate, one end of each of said first and second elongated planar conductive elements being continuous with said first and second separated planar conductive elements, respectively, for coacting with said third planar conductive element for defining feed transmission lines for said first and second separated planar conductive elements, the other end of each of said first and second elongated planar conductive elements being electrically coupled for corporate feed of said first and second separated conductive elements.

14. An array according to claim 11 further comprising bias means coupled to said first and second semiconductor diodes for controlling said capacitance.

15. An array according to claim 12 wherein said bias means comprises a source of direct voltage.

16. An array according to claim 13 further comprising low pass filter means coupled to said source of direct voltage and to said corporate feed.

18. An arrangement according to claim 15 wherein said first planar conductive element is a rectangular patch and said second planar conductive element is a ground plane.

19. An arrangement according to claim 15 wherein said one of said n and p is n.

23. An arrangement according to claim 15 further comprising biasing means coupled to said diode for controlling said capacitance.

25. An arrangement according to claim 15 further comprising an elongated planar conductive element attached to said first broad side of said substrate, one end of said elongated planar conductive element being electrically continuous with said first planar conductive element, said elongated planar conductive element coacting with said second planar conductive element to define a transmission line.

26. An arrangement according to claim 23 further comprising biasing means coupled to said diode for controlling said capacitance.

9. a third planar conductive element attached to said second broad side of said substrate;

and

10. at least first and second semiconductor P-N diodes, formed within said substrate, each of said first and second semiconductor diodes having associated capacitance and including first and second adjacent electrodes of opposite conductivity type, said first electrodes of said first and second semiconductor diodes being galvanically connected to said first and second planar conductive elements, respectively, and said second electrodes of said first and second semiconductor diodes being galvanically connected at different locations to said third planar conductive element for electrically connecting said first semiconductor diode between said first and third planar conductive elements and for electrically connecting said second semiconductor diode betwen said second and third planar conductive elements.

17. An antenna arrangement, comprising:

a planar substantially intrinsic semiconductor substrate including first and second broad sides;

a first planar conductive element attached to said first broad side of said substrate;

a second planar conductive element attached to said second broad side of said substrate;

at least one semiconductor P-N diode having associated capacitance and including first and second adjacent electrodes of opposite conductivity type formed within said substrate, said first electrode being galvanically connected to said first planar conductive element, and said second electrode being galvanically connected to said second planar conductive element for electrically connecting said diode between said first and second planar conductive elements;

wherein said semiconductor diode comprises a doped surface portion near the surface of said first broad side of said planar substantially intrinsic semiconductor suhbstrate, said doped surface portion including a first region which is heavily doped with one of n and p impurities, said first region lying under and being in contact with said first planar conductive element for forming an ohmic contact between said first planar conductive element and said doped surface portion; and

a conductive via hole extending between said first and second broad sides of said planar substantially intrinsic semiconductor substrate in a second region of said doped surface portion, said second region being heavily doped with the other of said n and p impurities for forming an ohmic contact between said doped surface portion and said via hole, thereby creating said semiconductor diode as a transverse diode in said doped surface portion.

20. An arrangement according to claim 17 wherein said semiconductor substrate is silicon, said n impurities are phosphorus ions and said p impurities are boron ions.

21. An arrangement according to claim 17 wherein said semiconductor substrate is gallium arsenide, said n impurities are silicon ions, and said p impurities are beryllium ions.

22. An arrangement according to claim 24 wherein said via hole has a conductive surface region formed from metallic gallium.

24. An arrangement according to claim 21 wherein said biasing means comprises a source of direct voltage.

27. An arrangement according to claim 24 wherein said biasing means comprises:

a source of direct voltage; and

low pass filter means coupled to said source of direct voltage and to a point along said elongated planar conductive element for coupling said direct voltage from said source of direct voltage to said diode by way of said elongated planar conductive element said first planar conductive elements, and for preventing significant amounts of signal from leaking from said elongated planar conductive element to said source of direct voltage.