Field-effect transistor having a delta-doped ohmic contact

• US 4,780,748 A
• Filed: 06/06/1986
• Issued: 10/25/1988
• Est. Priority Date: 06/06/1986
• Status: Expired due to Term

• Current Assignee: American Telephone & Telegraph Company (AT&T, Inc.), Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: American Telephone & Telegraph Company (AT&T, Inc.)
• Inventors: Cunningham, John E., Schubert, Erdmann F., Tsang, Won-Tien
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Limanek, Robert P.
• Application Number:
  US06/871,249
• Time in Patent Office: 872 Days
• Field of Search: 357/4, 357/4 SL, 357/22 A, 357/22 I, 357/22 K, 357/89, 357/90, 357/71
• US Class Current: 257/24
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02463 Arsenides
• CPC Class Codes: H01L 21/02499 Monolayers
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 29/0891 of field-effect transistors with Schottky gate
• CPC Class Codes: H01L 29/452 on AIII-BV compounds

Abstract

A field-effect transistor is created on a GaAs semi-insulating substrate using molecular beam epitaxy by fabricating a delta-doped monolayer with a silicon dopant between two undoped GaAs layers grown over the semi-insulating substrate. A plurality of delta-doped monolayers are grown over the surface of the upper undoped layer interleaved with layers of GaAs having a thickness equal to or less than the tunneling width of electrons in GaAs. A channel is etched through the plurality of delta-doped monolayers to permit a gate electrode to contact the upper undoped GaAs layer. Source and drain electrodes are deposited over the delta-doped monolayers on each side of the channel.

Claims

1. A field-effect transistor comprising a substrate of semi-insulating semiconductor material, first layer of said semiconductor material grown over said substrate, second layer of said semiconductor material grown over said first layer, at least one delta-doped monolayer having a predetermined dopant juxtaposed between said first and second semiconductor layers, and source, gate and drain electrodes fabricated from a metallic conducting material, characterized in that a plurality of delta-doped monolayers are interposed between said source and drain electrodes and said second semiconductor layer, said plurality of delta-doped monolayers being separated from each other and from the source and drain electrodes by layers of semiconductor material each one of which has a thickness equal to or less than the tunneling width of electrons in said semiconductor material, and said gate electrode is positioned in a channel that is cut through said plurality of delta-doped monolayers such that the gate electrode is in direct contact with said second semiconductor layer.

2. A field-effect transistor as defined in claim 1 wherein said semiconductor material is GaAs and said dopant is silicon.

3. A field-effect transistor comprising a semiconductor substrate, first and second semiconductor layers grown on said substrate, at least one delta-doped monolayer having a predetermined dopant juxtaposed between said first and second semiconductor layers, a channel etched in said second layer thereby defining ridges of semiconductor material on each of its sides, a gate electrode positioned in said channel, a plurality of delta-doped monolayers fabricated on the ridges on each side of said channel, and interleaved with layers of semiconductor material having a predetermined thickness, said predetermined thickness being equal to or less than the tunneling width of electrons in said semiconductor material, and metal electrodes positioned on said plurality of delta-doped layers on each side of said channel.

4. A field-effect transistor as defined in claim 3 wherein said semiconductor material is GaAs and said dopant is silicon.