Control flow computer using mode and node driving registers for dynamically switching between parallel processing and emulation of von neuman processors

• US 4,780,820 A
• Filed: 03/09/1987
• Issued: 10/25/1988
• Est. Priority Date: 11/07/1983
• Status: Expired due to Fees

• Current Assignee: Masahiro Sowa
• Original Assignee: Masahiro Sowa
• Inventors: Sowa, Masahiro
• Primary Examiner(s): Williams, Jr., Archie E.
• Assistant Examiner(s): Phung, Danh
• Application Number:
  US07/022,499
• Time in Patent Office: 596 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 712/1
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/4494 data driven

Abstract

A parallel processing computer comprises at least a memory for storing program as well as data and instructions for executing the program, a plurality of functional units, a node driving register for indicating executable instructions which are allowed to be executed by the functional units, and a mode register giving information to the functional unit as to whether the processing to be executed is of serial nature or parallel nature.

Claims

1. A parallel processing computer comprising:

a plurality of functional units (FU₁ . . . FU_n) for executing instructions in parallel with one another;

a memory (4) for storing said instructions and data to be utilized in execution of said instructions by said functional units;

a node driving register (1) for indicating instructions to be executed in parallel by said functional units, respectively;

a mode register means (2) connected to said functional units for storing information indicative of either a serial and parallel operation mode of said functional units; and

wherein said node driving register includes a plurality of node pointers, for serving as the program counter in a Von-Neuman processing operation, each of said node pointers (NPR) constituted by at least one word of said node driving register (1) designated by a given one of said functional units (FU₁, . . . , FU_n) connected with said mode register means, which is loaded with serial operation mode information and temporarily allocated for use only by said given one functional unit, to thereby serve as a program counter for a serial type operation of said given functional unit so that a serial type program is executed by said given one functional unit in cooperation with a node pointer and said memory.

2. A parallel processing computer as set forth in claim 1, said mode register means includes a plurality of mode registers (MD₁, . . . , MD_n) each connected to one of said plurality of function units (FU₁, . . . , FU_n), respectively, each mode register storing information indicative of either a parallel or serial operation mode in which the respective functional units are to execute respective instructions.

3. A parallel processing computer as set forth in claim 1, wherein execution of instruction is controlled by a token which simultaneously represents data to be used in executing said instruction.