Compilation using two-colored pebbling register allocation method such that spill code amount is invariant with basic block's textual ordering

• US 4,782,444 A
• Filed: 12/17/1985
• Issued: 11/01/1988
• Est. Priority Date: 12/17/1985
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Munshi, Ashfaq A., Schimpf, Karl M.
• Primary Examiner(s): Williams, Jr., Archie E.
• Assistant Examiner(s): Lee, Thomas C.
• Application Number:
  US06/809,989
• Time in Patent Office: 1,050 Days
• Field of Search: 364/200 MS File, 364/300, 364/900 MS File
• US Class Current: 717/153
• CPC Class Codes: G06F 8/441 Register allocation; Assignment of physical memory space to logical memory space

Abstract

A method for allocating and optimizing register assignments during compiling of source into executable code in either a scalar or vector processor uses a pebble game heuristic played on each basic block dependency graph for local optimization. Like variable analysis and loop unrolling are used for global optimization.

Claims

1. A method for allocating and optimizing register assignments during the compiling of source into executable code in either a scalar or a vector processor,

the source code including regions of code without branches termed "basic blocks", each basic block having statements defining computations,

each processor comprising memory for storing sequences of executable code and data, and means for accessing said memory and executing any accessed code;

the memory being mapped as a two-level model including a finite number p greater than 0 of registers and a comparably infinite internal memory, said registers having access times faster than that of internal memory,

comprising the processor-implemented steps of;

(a) ascertaining data dependency graph attributes of each basic block;

(b) generating a local register allocation and assignment for q of the p registers in the range 0<

q<

p with reference to all computations within each basic block by performing a "two-color pebbling game" heuristic over the ascertained data dependency graph utilizing the two-level memory model; and

(c) performing live variable analysis upon a flow graph-like representation of the basic blocks and responsively generating a global register allocation and assignment among (p-q) remaining registers assuming that loops expressed in the flow graph among the basic blocks are the most significant optimization entity.

2. A method according to claim 1, wherein the data dependency graph for each basic block is of the directed acyclic graph type.

3. A method according to claim 1, wherein the step of generating a local register allocation and assignment includes the steps of:

(b1) selecting the set of nodes of the graph which have the largest number of successors (dominators) in a leaf-to-root node direction;

(b2) ascertaining a cover cost of every node that is an immediate successor of the set chosen above, and assigning a register to that immediate successor in the set for which the cover cost is minimal; and

(b3) in the absence of any available allocatable registers, writing out an intermediate or final result signified by the computation at that node to internal memory and then subsequently loading said result back to an available register as required.

4. A method according to claim 1, wherein the step of generating a global register allocation and schedule includes:

(c1) generating a list for each variable and the frequency with which the variable is loaded or stored in the local allocations for these basic blocks weighted by the nesting level of that variable; and

(c2) selecting the variable having the highest frequency to reside in a global register, the steps of listing and selection being repeated until either no more of the (p-q) global registers are available, or the list is empty.

5. A method according to claim 1, wherein the step of performing live variable analysis and responsively allocating and assigning (p-q) registers globally includes the steps of ascertaining the "live ranges" for all variables not local to a basic block;

and allocating the variable with the largest live range to a global register, and in the event of two or more variables having the same live range, assigning one of the (p-q) registers to that variable having the largest number of uses or nesting level.