Self-testing memory

• US 4,782,486 A
• Filed: 05/14/1987
• Issued: 11/01/1988
• Est. Priority Date: 05/14/1987
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Maskas, Barry A., Morgan, David K., Lipcon, Jesse B.
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US07/049,812
• Time in Patent Office: 537 Days
• Field of Search: 371/21, 371/68, 364/200, 364/900
• US Class Current: 714/722
• CPC Class Codes: G11C 29/28 Dependent multiple arrays, e.g. multi-bit arrays

Abstract

A self-testing memory simultaneously writes test patterns into the memory banks of the memory, simultaneously compares the contents of one of the memory banks with the contents of the other of the banks, and records errors when the contents of the one memory bank differ from the contents of the other banks.

Claims

1. A self-testing memory composed of a plurality of independent memory banks and comprising:

means for simultaneously writing the same test patterns into corresponding locations in each of said plurality of memory banks;

means for accessing the contents at corresponding locations in each of said memory banks;

means for selecting one of said memory banks;

means for simultaneously comparing the contents at the locations of said selected one of said memory banks with the contents at corresponding locations of the others of said memory banks; and

means for recording, as errors, occurrences when the contents at the locations of said selected memroy banks are different from the contents at the corresponding locations of any of the others of said memory banks.

2. The self-testing memory of claim 1 wherein all of said memory banks reside on a single memory board.

3. The self-testing memory of claim 1 further including a plurality of memory board each including at least one of said plurality of memory banks.

4. The self-testing memory of claim 1 further including:

a first latch for holding the contents of said selected memory banks; and

a second latch for holding the contents of each of the others of said memory banks.

5. The self-testing memory of claim 4 wherein said sumultaneous comparing means includes a comparator coupled to said first and second latches.

6. The self-testing memory of claim 5 further including an OR gate coupled to said comparator.

7. The self-testing memory of claim 1 further including counting means for incrementing a count value each time the contents of the locations of said selected mmeory bank are different from the contents at the corresponding locations of any of the others of said memory banks.

8. The self-testing memory of claim 7 further including means for outputting the count value from said counting means.

9. A data processing system including a self-testing memory composed of a plurality of independent memory banks, said data processing system comprising:

means for simultaneously writing the same test patterns into corresponding locations in each of said plurality of memory banks;

means for accessing the contents at corresponding locations in each of said memory banks;

means for selecting one of said memory banks;

means, coupled to said memory, for examining the contents from said selected one of said memory banks to evaluate the operation of said memory;

means for simultaneously comapring the contents at the locations of said selected one of said memory banks with the contents at corresponding locations of each of the others of said memory banks; and

means for recording, as errors, occurrences when the contents at the locations of said selected memory bank are different from the contents at the corresponding locations of any of the others of said memory banks.

10. The data processing system of claim 9 further including:

a first latch for holding the contents of said selected one of said memory banks;

a second latch for holding the contents of each of the others of said memory banks; and

a comparator coupled to said first and second latches.

11. A self-testing memory system adapted to be coupled to a plurality of independent memory banks and comprising:

means for simultaneously writing the same test patterns into corresponding locations in each of said plurality of memory banks;

means for accessing the contents at corresponding locations in each of said memory banks;

means for selecting one of said memory banks;

means for simultaneously comparing the contents at the locations of said selected one of said memory banks with the contents at corresponding locations of each of the others of said memory banks; and

means for recording, as errors, occurrences when the contents at the locations of said selected memory banks are different from the contents at the corresponding locations of any of the others of said memory banks.

12. The self-testing memory system of claim 11 wherein all of said memory banks reside on a single memory board.

13. The self-testing memory system of claim 11 further including a plurality of memory boards each including at least one of said plurality of memory banks.

14. The self-testing memory system of claim 11 further including:

a first latch for holding the contents of said selected memory bank; and

a second latch for holding the contents of each of the others of said memory banks.

15. The self-testing memory system of claim 14 wherein said simultaneous comparing means includes a comparator coupled to said first and second latches.

16. The self-testing memory system of claim 15 further including an OR gate coupled to said comparator.

17. The selof-testing memory system of claim 11 further including counting means for incrementing a count value each time the contents at the locations of said selected memory bank are different from the contents at the corresponding locations of any of the others of said memory banks.

18. The self-testing memory system of claim 11 further including means, coupled to said memory system, for examining the contents from said selected memory banks to evaluate the operation of said memory system.

19. A self-testing memory system comprising:

a memory bus;

at least one memory board coupled to said memory bus and each including

a plurality of independent banks of memory,

transceiver circuits, each associated with a different one of said banks of memory, for causing data to be written into a selected location of the associated memory bank in response to a write signal and a corresponding one of a plurality of bank select signals,

a location detector circuit for producing a selected board signal if the board is in a selected board location,

a multiplexer, coupled to said location detector circuit and having inputs coupled to each of said banks on the memory board and an output coupled to said memory bus, for transferring the contents of a predetermined one of said banks to the memory bus if said location detector circuit produces said selected board signal,

a board latch for storing the contents from the predetermined one of said banks received from the memory bus,

bank latches for storing corresponding contents of each of said banks on the memory board,

a comparator having inputs coupled to said board latch and each of said bank latches, and

a counter having an input connected to the output of said comparator; and

a memory control circuit, coupled to each of said memory boards, for issuing said bank selected signals and said wirite signal, said memory control circuit including

a register for holding a test flag which is set when a fast memory diagnostic test is to be performed, and

a bank selected circuit for enabling all of said bank select signals simultaneously when said test flag is set.

20. A data processing system with self-testing memory capabilities comprising:

a memory bus;

at least one memory board coupled to said memory bus and each including

a plurality of independently banks of memory,

transceiver circuits, each associated with a different one of said banks of memory, for causing data to be written into a selected location of the associated memory banks in response to a write signal and a corresponding one of a plurality of bank select signals,

a location detector circuit for producing a selected board signal if the board is in a selected board location,

a muliplexer, coupled to said location detector circuit and having inputs coupled to each of said banks on the memory board and an output coupled to said memory bus, for transferring the contents of a predetermined one of said banks to the memory bus if said location detector circuit produces said selected board signal,

a board latch for storing the contents from the predetermined one of said banks received from the memory bus,

bank latches for storing corresponding contents of each of said banks on the memory board,

a comparator having inputs coupled to said board latch and each of said bank latches, and

a counter having an input connected to the output of said comparator;

a memory control circuit, coupled to each of said memory boards, for issuing said bank select signals and said write signal, said memory control circuit including

a register for holding a test flag which is set when a fast memory diagnostic test is to be performed, and

a bank select circuit for enabling all of said bank select signals simultaneously when said test flag is set; and

a central processing unit, coupled to said memory bus, for setting said test flag and for evaluating the contents from said predetermined memory bank.

21. A method for testing a memory composed of a plurality of independent memory banks, the method comprising the steps of:

writing the same test patterns into corresponding locations of said memory banks simultaneously;

accessing the contents at corresponding locations in each of said memory banks;

selecting one of said memory banks;

comparing the contents at the locations of said selected one of said memory banks with the contents at corresponding locations of each of the others of said memory banks simultaneously; and

recording, as errors, any differences in the contents at locations in said selected memory bank and the contents of corresponding locations of any of the others of said memory banks.

24. The method of claim 21 further including the steps of

reading the contents of said selected memory bank;

and

comparing the contents of said selected memory bank with the test patterns.

22. The method of 21 wherein said recording step includes the substep of counting the number of times that the contents at locations of said selected memory bank are different from the contents at corresponding locations of the other of said memory banks.

23. The method of 21 further including the step of repeating the writing and comparing steps with a plurality of different test patterns.

25. A method for testing a memory composed of a plurality of independent memory banks, the method comprising the steps of:

writing the same test patterns into corresponding locations of said memory banks simultaneously by simultaneously energizing memory select lines for each of said memory banks;

selecting one of said memory banks;

reading the contents at the locations of said selected one of said memory banks;

storing in a board latch the contents of the locations of said selected one of said memory banks;

reading the contents of the others of said memory banks simultaneously;

storing in bank latches the contents of the others of said banks simultaneously;

comparing the stored contents at locations of said selected memory bank with the stored contents at corresponding locations of each of the others of said memory banks simultaneously; and

recording, as errors, any occurrences when the stored contents at locations of said one memory bank differ from the stored contents of any of said others of said memory banks.

26. The method of claim 25 further including the steps of reading the contents of said selected memory bank;

and comparing the contents of said one memory bank with the test patterns.