Multichip integrated circuit packaging configuration and method

• US 4,783,695 A
• Filed: 09/26/1986
• Issued: 11/08/1988
• Est. Priority Date: 09/26/1986
• Status: Expired due to Term

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: General Electric Company
• Inventors: Eichelberger, Charles W., Wojnarowski, Robert J.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/912,456
• Time in Patent Office: 774 Days
• Field of Search: 357/71, 357/67, 357/75, 357/68
• US Class Current: 257/668
• CPC Class Codes: H01L 2224/2402 Laminated, e.g. MCM-L type
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/75315 Elastomer inlay
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A multichip integrated circuit package comprises a substrate to which is affixed one or more integrated circuit chips having interconnection pads. A polymer film overlying and bridging integrated circuit chips present is provided with a plurality of via openings to accommodate a layer of interconnection metallization which serves to connect various chips and chip pads within the interconnection pads disposed on the chips. A significant advantage of the packaging method and configuration of the present invention is the ability for the polymer film to be removed. This significantly improves testability and effectively provides wafer scale integration circuit packages which are free of problems associated with yield and testability.

Claims

1. A multichip integrated circuit package comprising:

a substrate;

a plurality of integrated circuit chips disposed on said substrate, said integrated circuit chips having interconnection pads thereon;

a polymer film overlying and bridging said integrated circuit chips, said polymer film having a plurality of via openings therein, said openings being aligned with at least some of said interconnection pads; and

a pattern of interconnection conductors disposed on top of said polymer film so as to extend between at least some of said openings and so as to provide electrical connection between at least some of said interconnection pads through said openings.

2. The integrated circuit package of claim 1 in which said film, together with said pattern of interconnection conductors, is removable.

3. The integrated circuit package of claim 1 in which said substrate comprises material selected from the group consisting of glass, metal, ceramic, plastic, silicon and composites.

4. The integrated circuit package of claim 1 in which said polymer film is selected from the group consisting of thermoplastic and thermoset materials.

5. The integrated circuit package of claim 1 further including

a second polymer film overlying said first polymer film and said interconnections, said second polymer film also including a plurality of via openings therein aligned with at least some of said interconnection patterns disposed on said first polymer film;

and

a second plurality of interconnection conductors disposed on said second film and extending between at least some of the openings in said second film so as to provide electrical connection between interconnection pattern conductors disposed on said first polymer film.

6. The integrated circuit package of claim 1 in which said interconnection conductor pattern includes a layer of titanium in contact with said polymer film.

7. The integrated circuit package of claim 6 in which said interconnection conductor pattern includes a layer of copper in contact with said titanium.

8. The integrated circuit package of claim 7 in which said copper layer is between about 3 and about 6 microns thick.

9. The integrated circuit package of claim 6 in which said titanium layer is approximately 1,000 angstroms thick.

10. An integrated circuit chip package comprising:

a substrate semiconductor;

at least one integrated circuit chip disposed on said substrate, said integrated circuit having interconnection pads thereon;

a polymer film overlying said at least one integrated circuit chip, said polymer film having a plurality of via openings therein, said openings being aligned with at least some of said interconnection pads; and

a pattern of interconnection conductors disposed on top of said polymer film so as to extend between at least some of said openings and so as to provide electrical connection to at least some of said interconnection pads through said openings.