Computer system for simulating reticular formation operation

• US 4,783,741 A
• Filed: 08/08/1984
• Issued: 11/08/1988
• Est. Priority Date: 08/08/1983
• Status: Expired due to Fees

• Current Assignee: Bernhard Mitterauer
• Original Assignee: Bernhard Mitterauer
• Inventors: Mitterauer, Bernhard
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): BUI, KIM T
• Application Number:
  US06/639,361
• Time in Patent Office: 1,553 Days
• Field of Search: 364/413, 364/300, 364/573, 128/906, 128/723
• US Class Current: 600/544
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: Y10S 128/923 by comparison of patient data to other data

Abstract

A system for simulation of the reticular formation is described. The system comprises as a central processing unit a command computer (4) structured on the basis of a permutograph and comprising a plurality of storage modules (M), with the storage modules (M) corresponding to the elements and the connections between the storage modules to the edges of the permutograph. The connections establish internal circuits which correspond to the negation sequences of the permutograph in the form of Hamilton loops (HK), there being associated with each Hamilton loop a behavior pattern of the reticular formation. The command computer (4) is controlled by input computers (1, 2, 3) in which a preprogrammed intended action is related to environmental information. The possibly new intended action computed therefrom is entered in the command computer (4) as a control command.

Claims

1. A computer system for simulating reticular formation operation comprising, in combination:

(a) an input computer for producing signals representing, respectively, both the actual environment and the intended action to be taken; and

(b) a command computer, connected to said input computer, for executing a program on the principle of a permutograph thereby to give effect to said intended action in dependence upon said environment, said command computer comprising;

(1) a plurality (n) of addressable storage modules (M-1, M-2, . . . M-i, . . . M-n), each storage module including a program sequence memory for storing, as a storage module address, a unique program sequence corresponding to at least one intended action, the different program sequences stored, respectively, in different program memories being permutations of each other; and

(2) means for connecting said storage modules together into closed circuits, called "Hamilton loops", each Hamilton loop forming a series connection of a plurality of storage modules in a specific permutation of said program sequences that identify said storage modules by address;

whereby a specific run through the storage modules in the sequence defined by a Hamilton loop prescribes a specific course of action to be taken to effect said intended action.

2. The computer system of claim 1, wherein said input computer includes:

(1) a perception computer for sensing the environment and producing signals representing environmental data; and

(2) an intended action computer for producing signals representing successive ones of a plurality of program sequences.

3. The computer system of claim 2, wherein said input computer further comprises a relations computer, connected to said perception computer and to said intended action computer, for weighting the environmental data from said perception computer according to a table set by the program sequences provided by said intended action computer, said relations computer producing signals representative of said weighting which are supplied to said command computer.

4. The computer system defined in claim 3, wherein said intended action computer computes from data programmed therein a first Hamilton loop sequence and produces signals representing said first Hamilton loop sequence;

and wherein said relations computer is responsive to said environmental data produced by said perception computer to compute a second Hamilton loop sequence with respect to the environmental data and to compare said second Hamilton loop sequence with said first Hamilton loop sequence produced by said intended action computer; and

wherein said connecting means of said command computer is responsive to said relations computer to connect said storage modules together in a particular Hamilton loop sequence determined in the comparison.

5. The computer system of claim 2, wherein said intended action computer computes from data programmed therein a Hamilton loop sequence.

6. The computer system of claim 2, wherein the perception computer (100) has a plurality of different sensors (S-v, S-6, S-a), the command computer (400) comprises the same number of command computers (4-1, 4-2, 4-3), all of the same construction and activated synchronously by a central clock (51), an established priority value being associated with the storage modules (M-i-1, M-i-2, M-i-3) located at the same places in different ones of the command computers, the storage module (M-i-1, M-i-2, M-i-3) of the command computers with the highest priority being activated.

7. The computer system of claim 2, wherein the intended action computer (300) has a timing control unit (323) for the time sequence of the intended actions thereof.

8. The computer system of claim 7, and further comprising an executive computer (500) connected to the command computer (400) for converting the commands of the command computer (400) into control signals for a motor and the timing control unit (323) of the intended action computer (300).

9. The computer system of claim 1, wherein each storage module of said command computer further includes a negation operator memory for storing a negation operator which, when executed, is capable of transforming the program sequence stored in the program memory of the associated storage module into another program sequence, the program sequence and the negation operator of each storage module defining the program sequence of the next successive storage module in a particular Hamilton loop.

10. The computer system of claim 9, wherein said command computer further comprises an output register and means for storing the negation operators associated with each Hamilton loop in said output register.

11. The computer system according to claim 9, wherein each said negation operator memory is addressable and has stored therein the negation operator for each Hamilton loop (HK1 to HK4) which defines, together with the address of its associated storage module, the address of the next storage module in the Hamilton loop.

12. The computer system according to claim 11, wherein each storage module further includes a switching section (35) connected to said negation operator memory for activating the next storage module in the respective Hamilton loop.

13. The computer system according to claim 12, wherein each storage module further includes:

an addressable program memory for storing the permutation of programmed sequences assigned to that storage module, said program memory of each storage module being connected to said input computer; and

a module control unit (41) connected to said program memory, for transforming the command computer, upon activation of the program memory, to a state that is defined by the program sequence stored in said program memory.

14. The computer system of claim 1, wherein each storage module (M-i) further comprises a priority memory (43) in which is stored a previously established priority value for each selected Hamilton loop, the priority memory being connected to the priority memories of the rest of the memory modules (M-i).

15. The computer system of claim 14, further comprising an output circuit (59) connected between the input computer (100, 200, 300), on one hand, and the command computer (400), on the other, having a priority selected logic which selects the program with the highest priority for the command computer (400).

16. The computer system of claim 1, wherein the command computer (400) further comprises a read-only memory (ROM1 to ROM4) for each selected Hamilton loop (HK1 to HK4) connected in matrix form and a clock (51) for sequentially addressing said read-only memories, the memory locations of said read-only memories being at intersections of address lines and output lines (55, 56, 57), such that at least the number of the particular storage module (M-i) and an associated operation value for the selected Hamilton loop are presented at different groups of the output lines (55, 56, 57) upon sequential activation of the address lines,

said output lines (55) carrying said numbers of the storage modules (M-i) being connected to one input of a comparator (58) the other input of which is connected to an output circuit (59) of the input computer (100, 200, 300) which supplies the number of the storage module (M) which is selected as the preferred storage module by the input computer (100, 200, 300),

the output of the comparator (58) as well as said output lines (56) carrying the number of said selected Hamilton loop of the memory modules (M) of the read-only memories (ROM1 to ROM4) being connected to a register-decoder circuit (60, 61, 62) an output (E) of which is connected to a releasing input of one of the read-only memories (ROM1 to ROM4, and

the output lines (57) carrying the operation values of the read-only memories (ROM1 to ROM4) being connected to an output register (37, 63), the output register (37, 63) having an address decoder (54) which, after a compete run of a Hamilton loop, prepares the sequence of operation associated with the latter.

17. The computer system of claim 16, wherein the output register (37, 63) comprises a shift register (37) controlled by the clock (51), the shift register (37) being connected to the output lines carrying operation values of Hamilton loops and having parallel outputs, and a dynamic acceptance register (63) having inputs connected to the parallel outputs of the shift register (37) for accepting the data therefrom under the control of the address decoder (54) after a complete run-through of a Hamilton loop.

18. The computer system of claim 17, wherein the register-decoder circuit (60, 61, 62) has a release input which is connected with the address decoder (54).

19. The computer system of claim 16, wherein the register-decoder circuit (60, 61, 62) has a release input which is connected with the address decoder (54).