×

Semiconductor integrated circuit device with built-in memories, and peripheral circuit which may be statically or dynamically operated

  • US 4,783,764 A
  • Filed: 11/25/1985
  • Issued: 11/08/1988
  • Est. Priority Date: 11/26/1984
  • Status: Expired due to Term
First Claim
Patent Images

1. A semiconductor integrated circuit device comprising:

  • an information processing circuit which is operated by a periodic timing signal;

    an electrically programmable read only memory which is coupled to said information processing circuit and which is accessed by either said information processing circuit to read data thereof or from outside of said semiconductor integrated circuit device to write data therein, wherein said electrically programmable read only memory has a memory array and a peripheral circuit and wherein said peripheral circuit is statically or dynamically operated to access said memory array when said electrically programmable read only memory is accessed by either said information processing circuit or from the outside of said semiconductor integrated circuit device; and

    a control circuit for setting an operation of said peripheral circuit of said electrically programmable read only memory so that said peripheral circuit is statically operated when said electrically programmable read only memory is accessed from the outside of said semiconductor integrated circuit device and said peripheral circuit is dynamically operated in response to said periodic timing signal when said electrically programmable read only memory is accessed by said information processing circuit,wherein said peripheral circuit includes a read circuit having;

    a sense amplifier made receptive to a data signal from said memory array and;

    a latch circuit made receptive to the output of said sense amplifier; and

    wherein said control circuit is operative to output a control signal for interrupting the operation current of said sense amplifier after read data has been latched by said latch circuit, and further comprising;

    a dummy memory array including a dummy data line; and

    a read circuit for said dummy memory array, wherein said read circuit detects an end of the data reading operation based on detecting a predetermined level on said dummy data line and provides an output signal based on detecting said predetermined level, andwherein said control circuit is responsive to the output of said read circuit to output a control signal for interrupting said sense amplifier operation based on the output signal of said read circuit.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×