Data processing system having pipeline arithmetic/logic units

• US 4,783,783 A
• Filed: 07/24/1986
• Issued: 11/08/1988
• Est. Priority Date: 07/29/1985
• Status: Expired due to Fees

• Current Assignee: Hitachi Computer Engineering Company Limited (Hitachi, Ltd.), Hitachi, Ltd.
• Original Assignee: Hitachi Computer Engineering Company Limited (Hitachi, Ltd.), Hitachi, Ltd.
• Inventors: Nagai, Seiji, Wakui, Fujio, Kainoh, Hiromichi, Nishiyama, Takaaki
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Beausoliel, Robert W.
• Application Number:
  US06/888,936
• Time in Patent Office: 838 Days
• Field of Search: 371/51, 371/12, 371/13, 371/16, 364/200 MS File, 364/900 MS File
• US Class Current: 714/17
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G06F 9/3865 using deferred exception handling, e.g. exception flags

Abstract

A data processing system includes a multistage pipeline arithmetic/logic operation unit for implementing an arithmetic or logic operation for sets of element data sequentially and storing operational results sequentially in a memory using a single instruction. Check information indicative of the presence or absence of a fault occurring in each stage of the pipeline operation unit is moved in synchronism with the advancement of stages of the pipeline operation unit. A request control unit for storing the operational result in the memory suppresses the storing of the operational result in the memory if check information indicates a fault of the operational result which is being stored in the memory. The request control unit issues storage requests, which are counted by a counter. The counter indicates the number of elements stored normally in the memory.

Claims

1. A data processing system in which a plurality of element data are subject to an arithmetic or logic operation sequentially by a single instruction and operational results for sets of said element data are stored sequentially in a memory by said instruction, comprising:

pipeline arithmetic and logic operation means including a plurality of stages connected in series are performing an arithmetic or logic operation specified by said instruction sequentially operating on said sets of element data while passing said sets of element data through said stages;

check information means for transmitting check information indicative of the presence or absence of a fault occurring in each of said stages in synchronism with the flow of said element data in said pipeline arithmetic and logic operation means;

request control means for issuing a store request to said memory each time an operational result of each set of element data is obtained while passing through said stages for sequentially storing said operational results of said respective sets of element data in said memory in response to a signal from said pipeline arithmetic and logic operation means; and

counter means for counting the number of store requests issued by said request control means,

said request control means including first suppressing means for suppressing the issuance of said store request in response to said check information being indicative of a fault in said operational result which is being stored in said memory.

2. A data processing system according to claim 1, wherein said check information means includes a plurality of latch means connected in series each corresponding to a stage of said pipeline arithmetic and logic operation means.

3. A data processing system according to claim 2, wherein said pipeline operation means includes stage control means for controlling advancement of said sets of element data through said plurality of stages of said pipeline arithmetic and logic operation means and for controlling latching of said check information in said latch means in synchronism with the advancement of said sets of element data.

4. A data processing system according to claim 3, wherein said request control means includes a store buffer for storing and outputting, in the order of entry, said operational results from said pipeline arithmetic and logic operation means, and latch means for storing, in the order of entry, said check information from check information means and for outputting, in the order of entry, said check information to said first suppressing means.

5. A data processing system according to claim 4, wherein said stage control means includes second suppressing means for suppressing the advancement of said sets of element data in response to said check information being indicative of a fault in an operational result which is being stored in said memory.