Self correcting single event upset (SEU) hardened CMOS register

• US 4,785,200 A
• Filed: 08/20/1987
• Issued: 11/15/1988
• Est. Priority Date: 08/20/1987
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Huntington, Robert C.
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US07/056,171
• Time in Patent Office: 453 Days
• Field of Search: 307/279, 307/296.4, 307/966.5, 377/115, 377/116, 377/117, 377/104, 377/77, 377/79, 377/30
• US Class Current: 327/203
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors

Abstract

A self correcting single event upset-hardened CMOS register comprises a master portion and a slave portion. The master portion is coupled to a source of data and includes a feedback means such that said master portion can store said data during the first phase of a bi-phase clock signal. A slave portion including a second feedback path, has an input coupled to the output of said master portion and has an output which comprises the output of the register. An odd plurality of inverters is placed in series in the feedback path so as to isolate each node which is a possible site for high-energy particle impingement from other nodes in the loop and to attenuate and delay any resulting impulses such that the state of the error pulse cannot be maintained thus permitting the slave loop to remain in the state determined by the preceding data pulse.

Claims

1. An improved register of the type wherein there is provided a master portion including a first feedback path, which master portion stores data during the first phase of a bi-phase clock signal, and a slave portion having an output and having an input coupled to said master portion including a second feedback path for storing said data during a second phase of said bi-phase clock signal, said slave portion including a series inverter and said second feedback path extending from the output of said series inverter to the input of series inverter, said master portion being isolated from said slave portion during said second phase, the improvement commprising:

a plurality of attenuation and delay means coupled in series in said second feedback path, said plurality of attenuation and the delay means comprising an odd plurality of series coupled inverters.

2. An improved register according to claim 1 wherein said series inverter has a gain bandwidth product which is high compared to that of each of said odd plurality of inverters.

3. An improved CMOS register according to claim 2 wherein said odd plurality of inverters comprises five inverters.

4. An improved register according to claim 1 wherein said register is a CMOS register.

5. A CMOS register, comprising:

a master portion having an input coupled to a source of data and having an output, said master portion for storing said data;

a slave portion having an input coupled to the output of said master portion and having an output, said slave portion including propagation means and feedback means, said feedback means coupled between the output of said propagation means and the input of said propagation means; and

a plurality of attenuation and delay means coupled in series in said feedback means, said plurality of attenuation and delay means comprising an odd plurality of inverters.

6. A register according to claim 5 wherein said propagation means comprises a propagation inverter.

7. A register according to claim 5 wherein said propagation inverter has a gain bandwidth product which is high compared to that of each of said odd plurality of inverters.