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Fair arbitration technique for a split transaction bus in a multiprocessor computer system

  • US 4,785,394 A
  • Filed: 09/19/1986
  • Issued: 11/15/1988
  • Est. Priority Date: 09/19/1986
  • Status: Expired due to Fees
First Claim
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1. In a computer system comprising a plurality of modules and bus means commonly connected to all of the modules for conducting information signals between the modules, each module including means for transmitting information signals as a transfer over the bus means and while doing so functioning as a master module, each module also including means for receiving the transfer of information signals from the bus means and while doing so functioning as a slave module, a predetermined number less than all of the plurality of modules including means for initiating a transfer over the bus means in response to exogenous or internally generated events and thereby functioning as an initiator module, each module of the plurality other than the initiator modules including means for transmitting a transfer on the bus means only in response to a previous transfer transmitted by an initiator module and thereby functioning as a responder module, means associated with each module for assigning a predetermined priority to each module, the priorities of each module being different from one another, each responder module having a higher priority than any initaitor module, mnans associated with each module for asserting a request signal indicative of the predetermined priority of that module upon that module desiring to become a master module for transmitting a transfer over the bus means, and an improved arbitration means connected to the bus means and responsive to the request signals and operative during each of a plurality of sequential arbitration time periods for determining which of the plurality of modules asserting request signals is to be granted exclusive access to the bus means as a master module for a bus predetermined time period to transmit a transfer to an addressed slave module, said improved arbitration means further comprising:

  • means responsive to a plurality of request signals and operative for issuing a pending signal upon receipt of two request signals asserted during one arbitration period;

    means associated with each initiator module not previously asserting a request signal and operative in response to the assertion fo the pending signal for inhibiting and assertion of its request signal until the pending signal is negated;

    means associated with each one responder module for asserting a re-try signal upon detecting an attempt by an initiator module to transmit a transfer to the one responder module while the one responder module is busy processing a previously transmitter transfer, each responder module asserting a re-try signal becoming a busy responder module;

    means associated with each initiator module which unsuccessfully attempted a transfer to a busy responder module for recognizing the re-try signal asserted by the busy responder module, each initiator module recognizing the re-try signal becoming a waiting initiator module;

    means associated with each busy responder module for asserting a ready signal when the busy responder module ceases being busy upon completing the processing of the previously transmitted transfer;

    means associated with each waiting initiator module for asserting its request signal upon receipt of the ready signal;

    means associated with each initiator module which is not a waiting initiator module for rescinding any request signal it may have been asserting upon the receipt of the ready signal; and

    means operative during each predetermined arbitration period and responsive to the request, pending and ready signals for first granting exclusive access to the bus means to responder modules asserting request signals in the order of their predetermined priorities without regard to the assertion of the request and pending signals from initiator modules, and for thereafter granting exclusive access to the bus means to those initiator modules asserting request signals in the order of their predetermined priorities durigg the predetermined arbitration period when no request signals from responder modules are asserted to thereby give priority to waiting initiator modules over the other initiator modules and to give priority to the non-waiting initiator modules on the basis of precedence in time of their asserted requests while the pending signal is asserted.

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