Fair arbitration technique for a split transaction bus in a multiprocessor computer system

• US 4,785,394 A
• Filed: 09/19/1986
• Issued: 11/15/1988
• Est. Priority Date: 09/19/1986
• Status: Expired due to Fees

• Current Assignee: Datapoint Corp. (Dynacore Holdings Corporation)
• Original Assignee: Datapoint Corp. (Dynacore Holdings Corporation)
• Inventors: Fischer, Michael A.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Kriess, Kevin A.
• Application Number:
  US06/909,773
• Time in Patent Office: 788 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/114
• CPC Class Codes: G06F 13/36 for access to common bus or bus system

Abstract

An arbitration techique for a split transaction bus of a computer system obtains higher data throughput as a result of giving responders (e.g. memories) absolute priority over initiators (e.g. processors and I/O adapters), as a result of assigning all responders a higher priority than any initiator. Precedence is also given to retrying initiators which failed to complete a transaction because the module to which the transfer was addressed was busy. The requests from non-retrying initiators are temporarily rescinded to give precedence to the requests from retrying initiators. There is an absolute limit or bound to the number of requests which a retrying module may make before it is granted mastership of the bus to accomplish its transfer. To accomplish test and set and memory scrub transactions with a minimum time loss, the bus of the computer system creates a null conductivity cycle immediately following the cycle in which the address of the memory location to be tested and set or scrubbed is transferred.

Claims

1. In a computer system comprising a plurality of modules and bus means commonly connected to all of the modules for conducting information signals between the modules, each module including means for transmitting information signals as a transfer over the bus means and while doing so functioning as a master module, each module also including means for receiving the transfer of information signals from the bus means and while doing so functioning as a slave module, a predetermined number less than all of the plurality of modules including means for initiating a transfer over the bus means in response to exogenous or internally generated events and thereby functioning as an initiator module, each module of the plurality other than the initiator modules including means for transmitting a transfer on the bus means only in response to a previous transfer transmitted by an initiator module and thereby functioning as a responder module, means associated with each module for assigning a predetermined priority to each module, the priorities of each module being different from one another, each responder module having a higher priority than any initaitor module, mnans associated with each module for asserting a request signal indicative of the predetermined priority of that module upon that module desiring to become a master module for transmitting a transfer over the bus means, and an improved arbitration means connected to the bus means and responsive to the request signals and operative during each of a plurality of sequential arbitration time periods for determining which of the plurality of modules asserting request signals is to be granted exclusive access to the bus means as a master module for a bus predetermined time period to transmit a transfer to an addressed slave module, said improved arbitration means further comprising:

means responsive to a plurality of request signals and operative for issuing a pending signal upon receipt of two request signals asserted during one arbitration period;

means associated with each initiator module not previously asserting a request signal and operative in response to the assertion fo the pending signal for inhibiting and assertion of its request signal until the pending signal is negated;

means associated with each one responder module for asserting a re-try signal upon detecting an attempt by an initiator module to transmit a transfer to the one responder module while the one responder module is busy processing a previously transmitter transfer, each responder module asserting a re-try signal becoming a busy responder module;

means associated with each initiator module which unsuccessfully attempted a transfer to a busy responder module for recognizing the re-try signal asserted by the busy responder module, each initiator module recognizing the re-try signal becoming a waiting initiator module;

means associated with each busy responder module for asserting a ready signal when the busy responder module ceases being busy upon completing the processing of the previously transmitted transfer;

means associated with each waiting initiator module for asserting its request signal upon receipt of the ready signal;

means associated with each initiator module which is not a waiting initiator module for rescinding any request signal it may have been asserting upon the receipt of the ready signal; and

means operative during each predetermined arbitration period and responsive to the request, pending and ready signals for first granting exclusive access to the bus means to responder modules asserting request signals in the order of their predetermined priorities without regard to the assertion of the request and pending signals from initiator modules, and for thereafter granting exclusive access to the bus means to those initiator modules asserting request signals in the order of their predetermined priorities durigg the predetermined arbitration period when no request signals from responder modules are asserted to thereby give priority to waiting initiator modules over the other initiator modules and to give priority to the non-waiting initiator modules on the basis of precedence in time of their asserted requests while the pending signal is asserted.

2. An invention as defined in claim 1 further comprising:

means for maintaining the assertion of the pending signal during the temporary rescission of request signals from non-waiting initiator modules.

3. An invention as defined in claim 2 further comprising:

means for asserting a hold signal upon a module obtaining bus exclusive access for the purpose of accomplishing a transaction which requires more than one bus period to accomplish a series of sequential transfers and wherein;

the arbitration means is responsive to the hold signal and is operative to prohibit the granting of bus exclusive access to a different module until negation of the hold signal.

4. An invention as defined in claim 1 further comprising:

means for asserting a hold signal upon a module obtaining bus exclusive access for the purpose of accomplishing a transaction which requires more than one bus period to accomplish a series of sequential transfers, and wherein;

the arbitration means is responsive to the hold signal and is operative to prohibit the granting of bus exclusive access to a different module until negation of the hold signal.

5. An invention as defined in claim 1 further comprising:

means for counting the number of times a request signal is asserted by a waiting initiator module before it is successful in transmitting the transfer waiting to transmit, and for asserting the pending signal after the count has exceeded a predetermined number, and for maintaining the pending signal until the waiting initiator module whose request signals were counted is granted exclusive access to the bus means.

6. An invention as defined in claim 1 wherein:

a ready signal is supplied to all waiting initiator modules from each responder module which ceases being busy.

7. An invention as defined in claim 1 wherein:

the means for asserting the request signals, for asserting the pending signal, for asserting the re-try signal, for asserting the ready signal, for temporarily rescinding the request signals, and for granting exclusive access to the bus means, are each associated with each module appropriate to the module type asserting such signals.

8. An invention as defined in claim 1 wherein:

the means for asserting the request signals, for asserting the pending signal, for asserting the re-try signal, for asserting the ready signal, for temporarily rescinding the request signals, and for granting exclusive access to the bus means, are included in each module appropriate to the module type asserting such signals.

9. An invention as defined in claim 1 wherein:

each module is physically connected to the bus means by means including an electrical connector, and

the electircal connectors are electrically interconnected with one another to establish the priority of each module according to the physical connector to which the module is connected

10. An invention as defined in claim 9 wherein each request signal from a module of higher priority is conducted to each module of lower priority.

11. An invention as defined in claim 1 further comprising:

means associated with each slave module and responsive to the transfer of information signals for providing a status signal indicative of the status of the transfer by the slave module, and wherein;

the periods of the bus means and of the arbitration means are at regular and uniform length time intervals, each time interval being a bus cycle;

the means for asserting the request and ready and re-try signals do so at predetermined points in each bus cycle;

the means for arbitrating bus exclusive access does so during a single bus cycle;

the first transfer of information signals over the bus means at one bus cycle is accomplished by the master module whose exclusive access to the bus means was established on the immediately preceding cycle; and

the means for supplying the status signal does so on the bus cycle after the one cycle in which the transfer of information signals occurs.

12. An invention as defined in claim 11 wherein:

the bus means transfers information signals on a split transactional basis, wherein the information signals transferred in a request for a read transaction is transferred in a bus cycle which is separated by at least one complete bus cycle from the bus cycle in which the read information is transferred back.

13. An invention as defined in claim 1 wherein:

the periods of the bus means and of the arbitrating means are at regular uniform length time intervals, each time interval being a bus cycle;

the information signals include a command for a read/modify/write operation which causes a memory of a responder module to functionally read the original data at a specific memory location and write predetermined data to the location and write the original data back to the module asserting the read/modify/write command; and

further comprising;

means for accomplishing a predetermined test and set operation at a predetermined location in a memory of a responder module by transferring a read/modify/write command from an initiator module to the memory of the responder module in one bus cycle; and

wherein

the memory of the responder module includes means for performing the read/modify/write command and for transferring the original data back during a bus cycle subsequent to the one cycle.

14. An invention as defined in claim 13 wherein at least one responder module to which the test and set operation is addressed includes a cache memory having coherence logic, and the means for arbitrating bus exclusive access further establishes a null condition over the bus means in the bus cycle next immediately following the bus cycle in which the command for a read/modify/write operation was transmitted to the cache memory to permit time for the coherence logic of the cache memory to operate.

15. In a computer system comprising initiator modules including at least one which is processor, responder modules including at least one which is a memory, a bus commonly connecting the modules, means for establishing bus cycles during which separate transfers of information signals are communicated between the modules, and means for arbitrating exclusive access of the bus to establish selected communication paths between a selected initiator and a responder addressed by the selected initiator;

and improved means for accomplishing test and set operations in the memory, comprising in combination;

means for transferring a command for a read/modify/write operation to the memory during one bus cycle;

said memory further includes means for performing a read/modify/write operation in response to the read/modify/write command to read the original data at an addressed memory location and write predetermined data to the addressed location and write the original data back, the writing of the original data back occurring during a bus cycle subsequent to the one bus cycle; and

said bus arbitrating means inhibiting communication over the bus for a bus cycle after the one bus cycle to allow the memory to write the predetermined data to the addressed location during the read/modify/write operation without being addressed by another command until after the predetermined data has been written to the addressed memory location.

16. An invention as defined in claim 15 wherein said means for arbitrating exclusive access to the bus creates a null communication condition on the bus during the next bus cycle which immediately follows the one bus cycle.

17. An invention as defined in claim 15 wherein said computer system also includes means for supplying signals over the bus indicative of predetermiined bytes of data which are enabled for computer operations in association with a transfer of that data, and the memory further includes means for correcting errors in the original data contained in memory locations;

and said improvement further includes means for accomplishing a memory scrub operation as a specific version of a test and set operation, comprising;

means associated with the memory and receptive of the byte enable signals for causing error corrected original data to be written back into the addressed memory location rather than writing back the predetermined data in performing the read/modify/write operation.

18. ln a computer system comprising a plurality of modules and bus means commonly connected to all of the modules for conducting information signals between the modules, each module including means for transmitting information signals as a transfer over the bus means and while doing so functioning as a master module, each module also including means for receiving the transfer of information signals from the bus means and while doing so functioning as a slave module, a predetermined number less than all of the plurality of modules including means for initiating a transfer over the bus means in response to exogenous or internally generated events and thereby functioning as an initiator module, each module of the plurality other than the initiator modules including means for transmitting a transfer on the bus means only in response to a previous transfer transmitted by an initiator module and thereby functioning as a responder module, means associated with each module for assigning a predetermined priority to each module, the priorities of each module being different from one another, each responder module having a higher priority than any initiator module, means associated with each module for asserting a request signal indicative of the predetermined priority of that module upon that module desiring to become a master module for transmitting a transfer over the bus means, and an improved arbitration means connected to the bus means and responsive to the request signals and operative during each of a plurality of sequential arbitration time periods for determining which of the plurality of modules asserting request signals is to be granted exclusive access to the bus means as a master module for a predetermined time period to transmit a transfer to an addressed slave module, said improved arbitration means further comprising:

means responsive to a plurality of request signals from initiator modules for issuing a pending signal upon receipt of two request signals asserted during one arbitration period;

means associated with each initiator module not previously asserting a request signal and operative in response to the assertion of the pending signal for inhibiting the assertion of its request signal until the pending signal is negated;

means associated with each responder module for asserting its request signal without regard to the assertion of the pending signal;

means operative during each predetermined arbitration period and responsive to the request and pending signals for first granting exclusive access to the bus means to responder modules asserting request signals in the order of their predetermined priorities without regard to the assertion of the pending signal or request signals from initiator modules, and for thereafter granting exclusive access to the bus means to each of a plurality of initiator modules asserting request signals during the one arbitration period in the order of their predetermined priorities until all of the initiator modules asserting request signals during the one arbitration period have been granted bus exclusive access and before request signals from any other initiator modules are asserted.

19. An invention as defiined in claim 18 further comprising:

means for asserting a hold signal upon a module obtaining bus exclusive access for the purpose of accomplishing a transaction which requires more than one bus period to accomplish a series of sequential transfers, and wherein;

the arbitration means is responsive to the hold signal and is operative to prohibit the granting of bus exclusive access to a different module until negation of the hold signal.

20. An invention as defined in claim 18 wherein:

the periods of the bus means and of the arbitration means are at regular and uniform length time intervals, each time interval being a bus cycle;

said means for asserting the pending signal operatively negates the pending signal one bus cycle before the last module of the plurality of modules which asserted request signals during the one arbitration period is granted exclusive access to the bus means, and

said initiator modules which were inhibited from asserting their request signals during the assertion of the pending signal all simultaneously assert their request signals during the bus cycle when said last one module is granted exclusive access to the bus means.

21. In a computer system comprising a plurality of modules and bus means commonly connected to all of the modules for conducting information signals between the modules, each module including means for transmitting information signals as a transfer over the bus means and while doing so functioning as a master module, each module also including means for receiving the transfer of information signals from the bus means and while doing so functioning as a slave module, a predetermined number less than all of the plurality of modules including means for initiating a transfer over the bus mans in response to exogenous or internally generated events and thereby functioning as an initiator module, each module of the plurality other than the initiator modules including means for transmitting a transfer on the bus means only in response to a previous transfer transmitted by an initiator module and thereby functioning as a responder module, means associated with each module for assigning a predetermined priority to each module, the priorities of each module being different from one another, each responder module having a higher priority than any initiator module, means associated with each module for asserting a request signal indictive of the predetermined priority of that module upon that module desiring to become a master module for transmitting a transfer over the bus means, and an improved arbitration means connected to the bus means and responsive to the request signals and operative during eaoh of a plurality of sequential arbitrtion time periods for determining which the plurality of modules asserting request signals is to be granted exclusive access to the bus means as a master module for a predetermined time period to transmit a transfer to an addressed slave module, said improved arbitration means further comprising:

means associated with each one responder module for asserting a re-try signal upon detecting an attempt by an initiator module to transmit a transfer to the one responder module while that one responder module is busy processing a previously transmitted transfer, each responder module asserting a re-try signal becoming a busy responder module;

means associated with each initiator module which unsuccessfully attempted to transfer to a busy responder module for recognizing the re-try signal asserted by the busy responder module, each initiator module recognizing the re-try signal becoming a waiting initiator module;

means associated with each busy responder module for asserting a ready signal when the busy responder module ceases being busy upon completing the processing of the previously transmitted transfer;

means associated with each waiting initiator module for asserting its request signal upon receipt of the ready signal;

means associated with each initiator module which is a non-waiting initiator module for rescinding any request signal it may have been asserting upon the receipt of the ready signal to allow waiting initiator modules precedence in the order of their predetermined priorities over non-waiting initiator modules.

22. An invention as defined in claim 21 further comprising:

means for counting the number of times a request signal is asserted by a waiting initiator module before it is successful in transmitting the transfer waiting to be transmitted, and for asserting a pending signal after the count has exceeded a predetermined number; and

means associated with each initiator module and operative in response to the pending signal for preventing the assertion of a request signal until the pending signal is negated, thereby preventing the assertion of new request signals from initiator modules until the waiting initiator module is granted exclusive access to the bus means.