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Current limited epld array

  • US 4,785,423 A
  • Filed: 01/22/1987
  • Issued: 11/15/1988
  • Est. Priority Date: 01/22/1987
  • Status: Expired due to Term
First Claim
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1. An erasable programmable logic device comprising:

  • a plurality of memory cells coupled to vrious input signal lines;

    a first bit line coupled to a first side of each of said memory cells;

    a second bit line coupled to a second side of each of said memory cells;

    a sensing amplifier coupled to said first bit line such that said sensing amplifier monitors current flow on said first bit line;

    current controlling means coupled to said second bit line wherein total current flow through said plurality of memory cells also flows through said sensing amplifier and said current controlling means;

    said current controlling means also coupled to said sensing amplifier such that said current flow determines a drive of said current controlling means for maintaining a predetermined current limit on said current flow.

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