Electronic locking system
First Claim
1. In an electronic locking system having a processor and an electrically erasable programmable read-only memory (EEPROM) and a random access memory (RAM) supported within said electronic locking system, said processor having address outputs electrically connected to address inputs of said EEPROM and of said RAM to address memory locations within said EEPROM and within said RAM, data inputs electrically connected to data inputs/outputs of said EEPROM and of said RAM to receive data from said EEPROM and from said RAM, and a high-impedence control input for transforming said address outputs of said processor to a high-impedence state and deactivating said processor inputs for isolating said processor, the improvement comprising:
- a connector electrically connected to said address inputs of said EEPROM, said data inputs/outputs of said EEPROM, and said high-impedence control input of said processor, andEEPROM programming means electrically connected to said connector for activating said high-impedence control input of said processor to deactivate said inputs of said processor and render said address outputs of said processor to a high-impedence state during a programming operation, and for solely transmitting address information and data to said address inputs and data inputs/outputs of said EEPROM, respectively during said programming information to write data into said EEPROM, said RAM being unaffected during said programming of said EEPROM.
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Accused Products
Abstract
A field programmable electronic locking system includes a processor and an electrically erasable programmable read-only memory (EEPROM). The processor has address outputs electrically connected to address inputs of the EEPROM to address memory locations within the EEPROM, data inputs electrically connected to data inputs/outputs of the EEPROM to receive data from the EEPROM, and a high-impedence control input for transforming the address outputs of the processor to a high-impedence state. An EEPROM programmer activates the high-impedence control input of the processor to render the address outputs of the processor to a high-impedence state during a programming operation, and transmits address information and data to the address inputs and data inputs/outputs of the EEPROM, respectively during the programming information to write data into said EEPROM. Consequently, the EEPROM need not be removed from its socket or printed circuit board during programming, and may be programmed in the field.
77 Citations
13 Claims
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1. In an electronic locking system having a processor and an electrically erasable programmable read-only memory (EEPROM) and a random access memory (RAM) supported within said electronic locking system, said processor having address outputs electrically connected to address inputs of said EEPROM and of said RAM to address memory locations within said EEPROM and within said RAM, data inputs electrically connected to data inputs/outputs of said EEPROM and of said RAM to receive data from said EEPROM and from said RAM, and a high-impedence control input for transforming said address outputs of said processor to a high-impedence state and deactivating said processor inputs for isolating said processor, the improvement comprising:
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a connector electrically connected to said address inputs of said EEPROM, said data inputs/outputs of said EEPROM, and said high-impedence control input of said processor, and EEPROM programming means electrically connected to said connector for activating said high-impedence control input of said processor to deactivate said inputs of said processor and render said address outputs of said processor to a high-impedence state during a programming operation, and for solely transmitting address information and data to said address inputs and data inputs/outputs of said EEPROM, respectively during said programming information to write data into said EEPROM, said RAM being unaffected during said programming of said EEPROM. - View Dependent Claims (2, 3, 4)
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5. In combination with a circuit board including a processor connected therein and means defining an electrically programmable read-only memory and a random access memory connected therein, said processor having address outputs connected to address inputs of each of said memory means to address memory locations within each of said memory means, data inputs connected to data inputs/outputs of each of said memory means to receive data from each of said memory means, and a high-impedence control input for transforming said address outputs of said processor to a high-impedence condition and deactivating said processor inputs for isolating said processor, the improvement comprising:
memory programming means electrically connected to said address inputs of said electrically read only memory of said memory means, said data inputs/outputs of said electrically read only memory of said memory means, and said high-impedence control input of said processor, for activating said high-impedence control input of said processor to render said data outputs and inputs of said processor to said high-impedence condition during a programming operation, and for transmitting address information and data solely to said address inputs and said data inputs/outputs of said electrically programmable read only memory of said memory means during said programming operation to write data into said electrically programmable read only memory of said memory means, said random access memory being unaffected during said programming operation. - View Dependent Claims (6, 7, 8, 9, 10, 13)
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11. A process for programming an electronic lock circuit board having a processor and a random access memory (RAM) an electrically erasable programmable read-only memory (EEPROM) connected therein, said processor having address outputs connected to address inputs of said EEPROM and RAM to address memory locations within said EEPROM and RAM, data inputs electrically connected to data inputs/outputs of said EEPROM and RAM to receive data from said EEPROM and RAM, and a high-impedance control input for transforming said address outputs of said processor to a high-impedence state and for deactivation of said processor inputs for isolating said processor, said process comprising the steps of:
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while said processor and said EEPROM are connected to said circuit board, attaching one end of an electrical connector to said address inputs of said EEPROM, to said data inputs/outputs of said EEPROM, and to said high-impedence control input of said processor, attaching an EEPROM programmer to the other end of said connector, and operating said EEPROM programmer to activate said high-impedence control input of said processor to render said address outputs and said inputs of said micro-processor to said high-impedence state during a programming operation, and transmit address information and data solely to said EEPROM during said programming operation to write data into said EEPROM, said RAM being unaffected during said programming operation. - View Dependent Claims (12)
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Specification