High voltage depletion mode MOS power field effect transistor

• US 4,786,952 A
• Filed: 07/24/1986
• Issued: 11/22/1988
• Est. Priority Date: 07/24/1986
• Status: Expired due to Fees

• Current Assignee: General Motors Corporation (Motors Liquidation Co. GUC Trust)
• Original Assignee: General Motors Corporation (Motors Liquidation Co. GUC Trust)
• Inventors: Jain, Kailash C., MacIver, Bernard A.
• Primary Examiner(s): Edlow, Martin H.
• Assistant Examiner(s): Josephs, David R.
• Application Number:
  US06/888,697
• Time in Patent Office: 852 Days
• Field of Search: 357/23.8, 357/23.4, 357/23.1, 357/45
• US Class Current: 257/260
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Abstract

A vertical depletion mode power field effect transistor having a greatly increased drain-to-source breakdown voltage. The drain region is formed in the substrate and separated from the channel by a first insulative layer having apertures which allow the passage of electrical currents. The channel, which is formed between the first insulative layer and a second insulative layer parallel to the substrate surface, contains both a source region, formed by implantation of impurities of the same type as are used to form the drain region, and a gate region. In this configuration, the normally high voltage which exists between the gate and drain is imposed over a greater distance than in conventional depletion mode vertical FETs, so that this new configuration produces vertical power FETs having much higher breakdown voltages than do conventional depletion mode vertical FETs. Islands having a conductivity type opposite to that used to form the source region are formed immediately below the second insulative layer and serve to prevent the creation of a charge inversion layer in the channel, where the inversion layer adversely affects the turn off characteristic of the j-MOS power transistor.

Claims

1. A vertical FET device having a high drain-to-source breakdown voltage, comprising:

a substrate of a semiconductor material of a first each of the source electrode apertures being doped with an impurity of the first conductivity type to form a more highly doped source region therein, and a second disjoint subset of said set of apertures not overlying said source regions, the portion of the third drain layer adjacent each aperture in said second subset of apertures being doped with an impurity of a conductivity type opposite to the first conductivity type;

one or more gate electrodes over the portion of the gate insulating layer adjacent said one or more source apertures;

an insulating layer over each of the gate electrodes, each said insulating layer being placed so as to leave one or more source regions in the third drain layer exposed through the source apertures; and

a source electrode layer for making electrical contact with each of the plurality of source regions in the epitaxial layer.

2. The vertical FET device of claim 1, wherein the surface of the second drain layer is substantially uniformly spaced from the substrate surface.

3. The vertical FET device of claim 2, wherein the apertures in said gate insulating layer are disposed substantially parallel to the first electrically insulating layer.

4. The vertical FET device of claim 1, wherein said source electrode layer is formed over said insulating layer over each gate electrode.

5. The vertical FET device of claim 1, wherein the apertures in the first insulating layer are elongated rectangles, said rectangles being substantially parallel along their longer side.

6. The vertical FET device of claim 5, wherein said second drain layer has a thickness of at least 3 micrometers.

7. The vertical FET device of claim 6, wherein the thickness of the third drain layer is in the range of 1.5 to 2 micrometers.

8. The vertical FET device of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

9. A vertical FET device having a high drain-to-source breakdown voltage, comprising:

a substrate of a semiconductor material of n conductivity type, said substrate having an n- surface and an n+ surface;

an n- drain region layer over the n- substrate surface, said n- drain region layer having a surface opposite from the substrate surface, said opposite drain region surface being substanitally uniformly spaced from the substrate surface by a distance of at least 3 micrometers;

a first electrically insulating layer of SiO₂, on the substrate surface spacing the drain region layer and the substrate surface apart in some but not all portions of its length and width, said insulating layer having one or more apertures therethrough in other portions, each of said apertures being an elongated rectangle, said rectangles being substantially parallel along their longer side;

said drain region layer contacting the substrate surface through said one or more rectangular apertures;

a gate insulating layer of SiO₂ over said surface of the drain region layer, said gate insulating layer having a set of apertures disposed substantially parallel to the first electrically insulating layer, a first subset of said apertures in said set of apertures being source region electrode apertures, said source region electrode apertures directly overlaying the drain region layer, the portion of the drain region layer adjacent each of the source region electrode apertures being doped with an n-type impurity to form a source region therein, said gate insulating layer further having a second disjoint subset of apertures, the portion of the drain region layer adjacent each aperture in said second subset of apertures being doped partially through its thickness to a p-type conductivity;

one or more gate electrodes over the portion of the gate insulating layer adjacent the second sheet of apertures;

an insulating layer of phosphosilicate glass over the gate electrodes, with said insulating layer having one or more apertures therein overlying the source region apertures in the gate insulating layer, effective to expose the surface of the source regions exposed through the source apertures in the gate insulating layer; and

a source electrode layer formed over said plurality of insulating layers for making electrical contact with each of the plurality of source regions exposed in the apertures in the insulating layer of phosphosilicate glass layer.