High power MOSFET with direct connection from connection pads to underlying silicon

• US 4,789,882 A
• Filed: 03/21/1983
• Issued: 12/06/1988
• Est. Priority Date: 03/21/1983
• Status: Expired due to Term

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Lidow, Alexander
• Primary Examiner(s): Clawson, Jr., Joseph E.
• Application Number:
  US06/477,012
• Time in Patent Office: 2,087 Days
• Field of Search: 53/23 C, 53/23 VD, 53/43, 53/48, 53/55, 53/68
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

The gate electrode pad and the source electrode pad of a high power MOSFET are supported atop an oxide layer. The peripheral regions of the source electrode which surround the areas of the gate and source pads are connected at a plurality of points around their peripheries through the oxide layer to the underlying silicon. This enables rapid collection of minority carriers which were weakly injected into the region surrounding the pads when a junction beneath the pads is forward-biased.

Claims

1. A metal oxide semiconductor field effect transistor comprising a semiconductor wafer, a plurality of base regions of one conductivity type symmetrically and laterally distributed over at least a portion of the area of one surface of said wafer;

at least the portion of said wafer receiving said plurality of base regions being of the other conductivity type;

a respective source region of said other conductivity type in each of said base regions, each of said source regions being laterally spaced from the periphery of their said respective base regions to define respective annular channel regions capable of inversion within their said respective base region;

an enlarged area base region of said one conductivity type;

said enlarged area base region laterally displaced from said plurality of base regions and extending to said one surface of said wafer;

an insulation layer overlying each of said channel regions and extending over said enlarged area base region;

conductive gate electrode means disposed atop said insulation layer and over each of said channel regions;

a source electrode means in contact with each of said source regions and in contact with each of said plurality of base regions;

a drain electrode connected to the opposite surface of said wafer;

an enlarged area source electrode pad continuous with said source electrode means and overlying said insulation layer which extends over said enlarged base region;

said source electrode pad having a peripheral region disposed adjacent said source electrode means; and

a plurality of spaced connection means electrically connecting respective portions of said source electrode pad adjacent to said periphery to said enlarged base region beneath said pad whereby said enlarged base region can efficiently collect minority carriers when said base regions are forward biased relative to said portion of said wafer which receives said plurality of base regions.

2. The transistor of claim 1 wherein said plurality of spaced connection means are generally equally spaced conductive projections from said source pad means which extend through said insulation layer and are connected to said enlarged base region.

3. The transistor of claim 1 wherein said insulation layer consists of silicon dioxide.

4. The transistor of claim 1 wherein said source electrode means and said source electrode pad consist of a single sheet of conductive material.

5. The transistor of claim 1 wherein said one conductivity type is the P type.

6. The transistor of claim 1 wherein the outer periphery of said base regions and of said respective source regions is polygonal.

7. The transistor of claim 6 wherein said outer periphery is hexagonal.