Interleaved pipeline parallel processing architecture

• US 4,789,927 A
• Filed: 04/07/1986
• Issued: 12/06/1988
• Est. Priority Date: 04/07/1986
• Status: Expired due to Term

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Hannah, Marc
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): CLARK, DAVID
• Application Number:
  US06/849,004
• Time in Patent Office: 974 Days
• Field of Search: 364/200, 364/900, 370/60, 370/94, 340/825.52
• US Class Current: 712/16
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead

Abstract

A system for processing of data wherein the data is inputted over time into the system such that a second packet of data is inputted before a first packet of data, the system comprising a first processor coupled to a second processor, the first processor operating on only the first packet of data and the second processor operating on only the second packet of data.

Claims

1. A system for processing of data, said data being inputted in a serial pipeline in a predetermined order into said system such that a second packet of data is inputted into said system before a first packet of data, said system comprising:

a system input in said serial pipeline;

a system output in said serial pipeline;

a first processor in said serial pipeline coupled to said system input for receiving said first and said second packets of data, said first processor receiving said second packet of data and passing said second packet of data to a second processor in said serial pipeline coupled to said first processor, said first processor receiving said first packet of data and performing a computational operation on said first packet of data, said first processor outputting the result of its operation on said first packet of data to said second processor, said first processor having a first means for assuring that said first processor operates on only said first packet of data and a means for assuring that said second packet of data is passed to said second processor before the result of the operation on said first packet of data is outputted to said second processor;

said second processor coupled to said system output, said second processor receiving said second packet of data and performing a computational operation on said second packet of data, said second processor outputting to said system output the result of its operation on said second packet of data, said second processor receiving the result of the operation of said first processor on said first packet of data, said second processor passing the result of the operation of said first processor on said first packet of data to said system output, said second processor having a second means for assuring that said second processor operates on only said second packet of data and means for assuring that the result on said second packet of data is outputted in time from said system before the result on said first packet of data is outputted from said system,

wherein said data is a stream of data having a repeating pattern of at least a first packet of data and a second packet of data and wherein said first means for assuring is a first modulo-N counter and said second means for assuring is a second modulo-N counter, where N is equal to the number of packets of data in said repeating pattern wherein said first processor only processes data when said first modulo-N counter is at a first specific predetermined value and said second processor only processes data when said second modulo-N counter is at a second specific predetermined value,

whereby both said first and second packets of data in the serial pipeline proceed through said first and said second processors and said first processor operates on only said first packet of data and said second processor operates on only said second packet of data.