Processing method of image data and system therefor

• US 4,790,025 A
• Filed: 09/26/1985
• Issued: 12/06/1988
• Est. Priority Date: 12/07/1984
• Status: Expired due to Fees

• Current Assignee: SCREEN Holdings Co., Ltd.
• Original Assignee: SCREEN Holdings Co., Ltd.
• Inventors: Miki, Shigeru, Inoue, Toshifumi, Yamada, Mitsuhiko
• Primary Examiner(s): Boudreau, Leo H.
• Assistant Examiner(s): Couso, Jose L.
• Application Number:
  US06/780,563
• Time in Patent Office: 1,167 Days
• Field of Search: 364/200, 364/731, 364/900, 358/22, 382/41-48, 340/723-724, 340/727, 340/731
• US Class Current: 382/293
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

The present invention makes it possible to reduce the processing time by dividing an image, which is to be subjected to a processing, into a plurality of sections and subjecting the thus-divided images to an image processing in a limited memory space, especially, by making most effective use of the memory spaces of plural buffer memories to reduce the number of divisions of the original picture when a high-speed affine transformation is performed in the plural buffer memories.

Claims

1. A method for processing data of an original picture, comprising the steps of:

(a) storing data as image data in a memory having a large capacity and a relatively low access speed;

(b) dividing at least one group of the data into a plurality of data portions, on the basis of a processble size, between two memories capable of performing writing and reading at high speeds;

(c) reading out the image data in each data portion from the low-speed memory to perform at least one type of image processing on the read-out image data between the two high-speed memories;

(d) storing the thus-processed image data against in the low-speed memory; and

(e) performing the above steps (b) through (d) repeatedly on all of the data of the original picture so as to store the processed data of the original picture in the large-capacity and low-speed memory;

wherein address control for each of the two high speed memories employed in the course of the image processings (b) through (e) is performed in accordance with a multidimensional array and addresses of one of the two high speed memories are identified by an affine transformation or inverse affine transformation of addresses of the other high speed memory, whereby the processing of the image data between the two high speed memories is performed in such a way that the image data, which is transferred between both high speed memories, is subjected to the affine transformation or the inverse affine transformation, wherein prior to subjecting the image data to the affine transformation between the two high speed memories, the address control of each of which is performed in accordance with the multidimensional array, the initial setting upon performing the processing of the image data between both high speed memories is effected by finding out the degree of overlapping between the two-dimensional address area of the high speed memory in which the image data before the affine transformation thereof are stored, and the two-dimensional address area of the high speed memory in which the affine-transformed image data are stored through the inverse affine transformation of the addresses of one of the high speed memories, changing the address length or lengths of the two-dimensional array or arrays of either one or both of the memories so as to optimize the overlapped area, obtaining parameter or parameters corresponding to the address length or lengths and then obtaining an affine coefficient by which the addresses of both high speed memories are corresponding to each other through inverse affine transformation.

2. A method according to claim 1, wherein address signals which are subjected to the affine transformation or the inverse affine transformation are multidimensionally-arrayed address signals adapted to perform the address control of the two memories.

3. A method according to claim 1 or 2, wherein addresses of the memory, which receives and stores image data, are successively identified in advance and then subjected to the inverse affine transformation so as to designate addresses of the memory to which the image data are sent, whereby image data to be subjected to the affine transformation for storage in the latter memory are retrieved on the memory from which the image data are sent out.

4. A method according to claim 1 or 2, wherein when the memory for the reception and storage of image data contains insufficient image data for the affine transformation and subsequent storage, image data to be stored in the memory for sending out image data are replaced by other image data so that the memory adapted to receive image data is filled with affine-transformed image data.

5. A method according to claim 1 or 2, wherein the processing of the image data effected between the two high speed memories is coordinate conversion which is effected by the affine transformation or inverse affine transformation to perform rotation, expansion, reduction, deformation or the like of the image.