Process for making a hermetic low cost pin grid array package

• US 4,791,075 A
• Filed: 10/05/1987
• Issued: 12/13/1988
• Est. Priority Date: 10/05/1987
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Lin, Paul T.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/104,478
• Time in Patent Office: 435 Days
• Field of Search: 437/209, 437/214, 437/217, 437/215, 437/220, 174/52 PE, 174/52 S, 174/52 H, 357/70, 361/404
• US Class Current: 29/837
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/057 the leads being parallel to the base
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/0132 Binary Alloys
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: Y10T 29/49139 : by inserting component lead or terminal into base aperture
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49153 : with shaping or forcing terminal into base aperture
• CPC Class Codes: Y10T 29/49162 : by using wire as conductive path

Abstract

A process for making hermetic, low cost pin grid array (PGA) semiconductor die packages. The process involves die bonding a semiconductor die or integrated circuit chip to a substrate having an interconnect or metallization pattern thereon. The die is electrically connected to the pattern and then the die and the inner bonds are hermetically sealed inside a cap that is smaller than the substrate so that the ends of the metallization pattern are exposed. The leads are then electrically connected, such as by solder or other technique to the exposed ends of the pattern.

Claims

1. A process for the assembling of a hermetic low cost pin grid array (PGA) semiconductor die package comprising the steps of:

providing an insulative substrate having a central die bonding area and a periphery, and a conductive pattern comprising a plurality of conductive material traces extending from the central die bonding area at their proximal ends to the periphery at their distal ends;

bonding a semiconductor die having a plurality of bonding pads thereon to the central die bonding area;

electrically connecting the bonding pads of the semiconductor die to the proximal ends of the conductive material traces;

hermetically sealing a cap onto the insulative substrate wherein the cap covers the semiconductor die and the proximal ends of the conductive material traces, leaving exposed the distal ends of the traces; and

affixing leads to the distal ends of the conductive material traces after the cap is hermetically sealed to the substrate, whereby the leads are in a position perpendicular to the conductive material traces,

in the absence of a plastic encapsulation step.

2. The process of claim 1 wherein the leads are metal pins.

3. The process of claim 1 wherein the leads are solder columns.

4. The process of claim 1 wherein the insulative substrate is of a single layer substrate.

5. The process of claim 1 wherein the electrical connection of the bonding pads of the semiconductor die to the proximal ends of the conductive material traces is achieved by wire bonding.

6. The process of claim 1 wherein the electrical connection of the bonding pads of the semiconductor to the proximal ends of the conductive material traces is accomplished at the same time as the bonding of the semiconductor die to the central die bonding area by means of flip chip bonding.

7. The process of claim 1 wherein the affixing of the leads to the distal ends of the conductive material traces is achieved by soldering.

8. A process for the assembling of a hermetic low cost pin grid array (PGA) semiconductor die package comprising the steps of:

providing a ceramic substrate having a central die bonding area, a plurality of lead holes at the periphery of the substrate piercing the substrate and a conductive pattern comprising a plurality of conductive material traces extending from the central die bonding area at their proximal ends to the lead holes at their distal ends;

bonding a semiconductor die having a plurality of bonding pads thereon to the central die bonding area;

electrically connecting the bonding pads of the semiconductor die to the proximal ends of the conductive material traces;

hermetically sealing a cap onto the ceramic substrate wherein the cap covers the semiconductor die and the proximal ends of the conductive material traces, leaving exposed the distal ends of the traces and the lead holes;

placing leads in the lead holes in a position perpendicular to the conductive metal traces; and

electrically affixing leads placed in the lead holes in the distal ends of the conductive material traces after the cap is hermetically sealed to the substrate,

in the absence of a plastic encapsulation step.

9. The process of claim 8 wherein the leads are metal pins.

10. The process of claim 9 wherein the leads are mechanically swaged into the lead holes prior to the semiconductor die bonding step.

11. The process of claim 9 wherein the leads are mechanically swaged into the lead holes after the cap is hermetically sealed onto the ceramic substrate.

12. The process of claim 8 wherein the leads are solder columns which are attached to the lead holes and the distal ends of the conductive material after the cap is hermetically sealed onto the ceramic substrate.

13. The process of claim 8 wherein the ceramic substrate is of a single layer substrate.

14. The process of claim 8 wherein the electrical connection of the bonding pads of the semiconductor die to the proximal ends of the conductive material traces is achieved by wire bonding.

15. The process of claim 8 wherein the electrical connection of the bonding pads of the semiconductor to the proximal ends of the conductive material traces is accomplished at the same time as the bonding of the semiconductor die to the central die bonding area by means of flip chip bonding.

16. The process of claim 8 wherein the affixing of the leads to the distal ends of the conductive material traces is achieved by soldering.

17. A process for the assembling of a hermetic low cost pin grid array (PGA) semiconductor die package comprising the steps of:

providing a ceramic substrate having a central die bonding area, a plurality of lead holes at the periphery of the substrate piercing the substrate and a conductive pattern comprising a plurality of conductive material traces extending from the central die bonding area at their proximal ends to the lead holes at their distal ends;

bonding a semiconductor die having a plurality of bonding pads thereon to the central die bonding area;

electrically connecting the bonding pads of the semiconductor die to the proximal ends of the conductive material traces;

hermetically sealing a cap onto the ceramic substrate wherein the cap covers the semiconductor die and the proximal ends of the conductive material traces, leaving exposed the distal ends of the traces and the lead holes;

placing leads into the lead holes in a position perpendicular to the conductive metal traces after the cap is hermetically sealed to the substrate; and

soldering the leads in the lead holes to the distal ends of the conductive material traces,

in the absence of a plastic encapsulation step.

18. The process of claim 17 wherein the leads have lead ends, and the leads are placed into the lead holes such that the lead ends are on the same side of the substrate as the semiconductor die.

19. The process of claim 17 wherein the leads have lead ends and socket holes in opposite ends thereof for receiving the lead ends from another package.