Latch-up protection circuit for integrated circuits using complementary MOS circuit technology

• US 4,791,316 A
• Filed: 03/13/1987
• Issued: 12/13/1988
• Est. Priority Date: 09/26/1986
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Siemens AG
• Inventors: Reczek, Werner, Pribyl, Wolfgang, Winnerl, Josef
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): HUDSPETH, DAVID R
• Application Number:
  US07/025,655
• Time in Patent Office: 641 Days
• Field of Search: 307/362-363, 307/ 496-497, 307/246, 307/572, 307/584-585, 307/296 R, 307/297, 361/86, 361/92, 361/100-101, 357/42, 357/38, 357/23.6, 365/226
• US Class Current: 327/545
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Abstract

A latch-up protection circuit for an integrated circuit using complementary MOS circuit technology has a substrate bias generator that applies a negative substrate bias to a semiconductor substrate having a p-conductive material into which a well-shaped semiconductor zone of n-conductive material is inserted. In order to avoid latch-up effects in the integrated circuit, an electronic protection circuit interrupts the capacitive charging currents of a capacitor in the substrate depending on the potential of the semiconductor substrate which is taken at a doped substrate bias terminal. The electronic protection circuit disconnects a capacitor bias generator from the capacitor when a voltage on the substrate bias terminal is greater than a difference between a reference potential and a threshold voltage of a first transistor in the electronic protection circuit. The electronic protection circuit connects the capacitive bias generator to the capacitor when a voltage on the substrate bias terminal is lower than the difference. No quiescent current flows through the electronic protection circuit during normal operation of the integrated circuit.

Claims

1. A latch-up protection circuit for use in integrated circuits using complementary MOS circuit technology, the integrated circuit having a substrate bias terminal and a doped semiconductor substrate, the substrate biased terminal connected to an output of a substrate bias generator, comprising:

a capacitor having first and second capacitor surfaces, said first surface integrated in the semiconductor substrate;

an electronic protection circuit connected to the substrate biased terminal and controlled by a voltage thereon, said electronic protection circuit also connected to said second surface of said capacitor, said electronic protection circuit having at least a first transistor with a predetermined threshold voltage; and

a capacitor bias generator for providing a predetermined voltage connected to said electronic protection circuit, said electronic protection circuit disconnecting said capacitor bias generator from said second surface of said capacitor when a voltage on the substrate bias terminal is greater than a difference between a reference potential and said threshold voltage of said first transistor in said electronic protection circuit, and said electronic protection circuit connecting said capacitor bias generator to said second surface of said capacitor when a voltage on the substrate bias terminal is less than said difference.

2. The latch-up protection circuit described in claim 1, wherein the semiconductor substrate has at least a well-shaped semiconductor zone of a first conductivity type, the semiconductor substrate having a second conductivity type, said well-shaped semiconductor zone of said first conductivity type inserted into said semiconductor substrate of said second conductivity type, the substrate bias terminal and said first surface of said capacitor located in said well-shaped semiconductor zone.

3. The latch-up protection circuit described in claim 1, wherein said electronic protection circuit comprises:

means for comparing said voltage on the substrate bias terminal to said difference between said reference potential and said threshold voltage of said first transistor;

means for amplifying having an input connected to an output of said means for comparing; and

means for electronic switching having an input connected to an output of the means for amplifying and also connected to said second surface of said capacitor and to said capacitor bias generator.

4. The latch-up protection circuit described in claim 3, wherein said means for comparing comprises:

a first input connected to the substrate bias terminal;

a second input connected to said reference potential;

a load element having a first terminal connected to a predetermined positive supply voltage; and

said first field effect transistor having a first terminal and a substrate terminal connected to said first input, a gate terminal connected to said second input and a second terminal connected to a second terminal of said load element, said load element and said first field effect transistor thereby being in series.

5. The latch-up protection circuit described in claim 4, wherein said means for electronic switching comprises p-channel field effect transistor having a gate connected to said second terminal of said load element, a substrate terminal connected to said positive supply voltage, a drain connected to said second surface of said capacitor and a source connected to said capacitor bias generator.

6. A latch-up protection circuit described in claim 5, wherein said load element is the gate capacitance of said p-channel field effect transistor.

7. The latch-up protection circuit described in claim 4, wherein said means for electronic switching comprises:

an inverter having an input connected to said second terminal of said load element and having an output; and

an n-channel field effect transistor having a gate connected to said output of said inverter, a substrate terminal connected to the output of the substrate bias generator, a source connected to said second surface of said capacitor and a drain connected to said capacitor bias generator.

8. The latch-up protection circuit described in claim 4, wherein said load element comprises a second field effect transistor having a channel type different from a channel type of said first field effect transistor, and having a gate connected to said gate of said first field effect transistor, a first terminal and a substrate terminal connected to said positive supply voltage and a second terminal connected to said second terminal of said first field effect transistor.

9. The latch-up protection circuit described in claim 4, wherein said load element is a capacitor.

10. The latch-up protection circuit described in claim 9, wherein said capacitor is a third field effect transistor having a different channel type from a channel type of said first field effect transistor, and having a source, a drain and a substrate terminal connected to said positive supply voltage, and having a gate connected to said gate of said first field effect transistor.

11. The latch-up protection circuit described in claim 1, wherein said latch-up protection circuit further comprises second means for providing an electronic switch controlled by voltage on the substrate bias terminal and having an input also connected to the substrate bias terminal and an output connected to said reference potential.

12. The latch-up protection circuit described in claim 11, wherein the substrate bias generator, said capacitor bias generator, said electronic protection circuit and said second means for providing an electronic switch are co-integrated on the semiconductor substrate.

13. A latch-up protection circuit for use in integrated circuits using complementary MOS circuit technology, the integrated circuit having a substrate bias terminal in a doped semiconductor substrate, the substrate bias terminal connected to an output of a substrate bias generator, comprising:

a capacitor having first and second capacitor surfaces, said first surface integrated in the semiconductor substrate;

an electronic protection circuit having a first input connected to the substrate bias terminal and a second input connected to a reference potential, having a load element with a first terminal connected to a predetermined positive supply voltage, having at least a first field effect transistor with a first terminal and a substrate terminal connected to said first input, a gate terminal connected to said second input and a second terminal connected to a second terminal of said load element, said load element and said first field effect transistor thereby being in series, and having a p-channel field effect transistor with a gate connected to said second terminal of said load element, a substrate terminal connected to said positive supply voltage, a drain connected to said second surface of said capacitor and a source terminal, said first field effect transistor having a predetermined threshold voltage; and

a capacitor bias generator for providing a predetermined voltage connected to said source terminal of said p-channel field effect transistor in said electronic protection circuit, said electronic protection circuit disconnecting said capacitor bias generator from said second surface of said capacitor when a voltage on the substrate bias terminal is greater than a difference between said reference potential and said threshold voltage of said first field effect transistor, and said electronic protection circuit connecting said capacitor bias generator to said second surface of said capacitor when the voltage on the substrate bias terminal is less than said difference.

14. The latch-up protection circuit described in claim 13, wherein said load element comprises a second field effect transistor having a channel type different from a channel type of said first field effect transistor, and having a gate connected to said gate of said first field effect transistor, a first terminal and a substrate terminal connected to said positive supply voltage and a second terminal connected to said second terminal of said first field effect transistor.

15. The latch-up protection circuit described in claim 13, wherein said load element is a third field effect transistor having a channel type different from a channel type of said first field effect transistor, and having a source, a drain, and a substrate terminal connected to said positive supply voltage, and having a gate connected to said gate of said first field effect transistor.

16. The latch-up protection circuit described in claim 13, wherein said load element is the gate capacitance of said p-channel field effect transistor.

17. The latch-up protection circuit described in claim 13, wherein said latch-up protection circuit further comprises a second means for providing an electronic switch controlled by the voltage on the substrate bias terminal and having an input also connected to the substrate bias terminal and an output connected to said reference potential.

18. A latch-up protection circuit for use in integrated circuits using complementary MOS circuit technology, the integrated circuit having a substrate bias terminal in a doped semiconductor substrate, the substrate bias terminal connected to an output of a substrate bias generator, comprising:

a capacitor having first and second capacitor surfaces, said first surface integrated in the doped semiconductor substrate;

an electronic protection circuit having a first input connected to the substrate bias terminal and a second input connected to a reference potential, having a load element with a first terminal connected to a predetermined positive supply voltage, having at least a first field effect transistor with a first terminal and a substrate terminal connected to said first input, a gate terminal connected to said second input, and a second terminal connected to a second terminal of said load element, said load element and said first field effect transistor thereby being in series and said first field effect transistor having a predetermined threshold voltage;

an inverter having an input connected to said second terminal of said load element and having an output;

an n-channel field effect transistor having a gate connected to said output of said inverter, a substrate terminal connected to the output of the substrate bias generator, a source connected to said second surface of said capacitor and a drain; and

a capacitor bias generator for providing a predetermined voltage connected to said drain of said n-channel field effect transistor in said electronic protection circuit, said electronic protection circuit disconnecting said capacitor bias generator from said second surface of said capacitor when a voltage on the substrate bias terminal is greater than a difference between said reference potential and said threshold voltage of said first field effect transistor, and said electronic protection circuit connecting said capacitor bias generator to said second surface of said capacitor when a voltage on the substrate bias terminal is lower than said diference.

19. The latch-up protection circuit described in claim 18, wherein said load element comprises a second field effect transistor having a channel type different from a channel type of said first field effect transistor, and having a gate connected to said gate of said first field effect transistor, a first terminal and a substrate terminal connected to said positive supply voltage and a second terminal connected to said second terminal of said first field effect transistor.

20. The latch-up protection circuit described in claim 18, wherein said load element is a third field effect transistor having a channel type different from a channel type of said first field effect transistor, and having a source, a drain and a substrate terminal connected to said positive supply voltage, and having a gate connected to said gate of said first field effect transistor.

21. The latch-up protection circuit described in claim 18, wherein said latch-up protection circuit further comprises second means for providing an electronic switch controlled by the voltage on the substrate bias terminal and having an input also connected to the substrate bias terminal and an output connected to said reference potential.