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Latch-up protection circuit for integrated circuits using complementary MOS circuit technology

  • US 4,791,316 A
  • Filed: 03/13/1987
  • Issued: 12/13/1988
  • Est. Priority Date: 09/26/1986
  • Status: Expired due to Term
First Claim
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1. A latch-up protection circuit for use in integrated circuits using complementary MOS circuit technology, the integrated circuit having a substrate bias terminal and a doped semiconductor substrate, the substrate biased terminal connected to an output of a substrate bias generator, comprising:

  • a capacitor having first and second capacitor surfaces, said first surface integrated in the semiconductor substrate;

    an electronic protection circuit connected to the substrate biased terminal and controlled by a voltage thereon, said electronic protection circuit also connected to said second surface of said capacitor, said electronic protection circuit having at least a first transistor with a predetermined threshold voltage; and

    a capacitor bias generator for providing a predetermined voltage connected to said electronic protection circuit, said electronic protection circuit disconnecting said capacitor bias generator from said second surface of said capacitor when a voltage on the substrate bias terminal is greater than a difference between a reference potential and said threshold voltage of said first transistor in said electronic protection circuit, and said electronic protection circuit connecting said capacitor bias generator to said second surface of said capacitor when a voltage on the substrate bias terminal is less than said difference.

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