Dense vertical j-MOS transistor

• US 4,791,462 A
• Filed: 09/10/1987
• Issued: 12/13/1988
• Est. Priority Date: 09/10/1987
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Blanchard, Richard A., Cogan, Adrian I.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US07/095,481
• Time in Patent Office: 460 Days
• Field of Search: 357/23.4, 357/23.14, 357/23.12, 357/22 D, 357/22 E
• US Class Current: 257/260
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

A j-MOS structure is disclosed which operates at high current densities and provides high current handling capability. A heavily doped N+ substrate, acting as a drain, has grown on it a lightly doped N- epitaxial layer. Within the epitaxial layer are multiple N+ buried regions, each within a corresponding P+ buried region, and bisecting each of the multiple N+ regions are vertical gates extending from the upper surface of the epitaxial layer down into the N+ substrate. These gates are insulated from the epitaxial layer and substrate via a thin gate oxide layer, but are electrically connected to the multiple N+ buried regions. Between each adjacent gate pair, N+ source regions are formed on the upper surface of the epitaxial layer. The gates are connected together via a conductive layer which also electrically shorts the gates to a poly-Si contact making contact with the N+ buried regions. The N+ source regions between the gates are also electrically connected together via the conductive layer, but are insulated from the gates and P+ and N+ buried regions.

Claims

1. A vertical transistor comprising:

a highly doped semiconductor substrate of a first conductivity type;

an epitaxial layer of a first conductivity type overlying said substrate;

one or more conductive gates insulated from said substrate and said epitaxial layer, each of said one or more gates being embedded fully within said epitaxial layer and partially within said substrate, the portions of said epitaxial layer being depleted by action of said one or more gates forming one or more vertical channels; and

one or more highly doped regions of a first conductivity type, each overlying a corresponding one of said one or more channels.

2. The vertical transistor of claim 1 further comprising:

one or more buried regions of a second conductivity type within said epitaxial layer, said one or more buried regions being in electrical contact with said one or more gates and sufficiently proximate to said one or more channels so as to sink minority carriers within said one or more channels.

3. The vertical transistor of claim 2 wherein said epitaxial layer is more lightly doped than said substrate.

4. The vertical transistor of claim 3 wherein said substrate acts as a drain of said transistor, and said one or more highly doped regions o a first conductivity type act as a source of said transistor.

5. The vertical transistor of claim 3 wherein said substrate acts as a source of said transistor and said one or more highly doped region of a first conductivity type act as a drain of said transistor.

6. The vertical transistor of claim 1 further comprising:

one or more buried regions of a second conductivity type within said epitaxial layer, said one or more buried regions being in rectifying contact with said one or more gates and sufficiently proximate to said one or more channels so as to sink minority carriers within said one or more channels.

7. The vertical transistor of claim 1 further comprising one or more buried regions of a first conductivity type, each within a corresponding buried region of a second conductivity type within said epitaxial layer, said one or more buried regions of a first conductivity type being in electrical contact with said one or more gates, and said one or more buried regions of a second conductivity type being sufficiently proximate to said one or more channels so as to sink minority carriers within said one or more channels.

8. A vertical transistor comprising:

a highly doped semiconductor substrate of a first conductivity type having bottom and top major surfaces;

an epitaxial layer of a first conductivity type overlying said substrate;

a plurality of conductive gates in electrical contact with each other and insulated from said substrate and said epitaxial layer, each of said gates having two major essentially parallel surfaces, said gates being embedded fully within said epitaxial layer and partially within said substrate such that said major parallel surfaces are essentially perpendicular to said major surfaces of said substrate, the portion of said epitaxial layer between facing surfaces of proximate gates forming one or more vertical channels; and

one or more highly doped regions of a first conductivity type, each overlying a corresponding one of said channels.

9. The vertical transistor of claim 8 further comprising:

one or more buried regions of a second conductivity type within said epitaxial layer, said one or more buried regions being in electrical contact with said gates and sufficiently proximate to said one or more channels so as to sink minority carriers within said one or more channels.

10. The vertical transistor of claim 9 wherein said epitaxial layer is more lightly doped than said substrate.

11. The vertical transistor of claim 10 wherein said substrate acts as a drain of said transistor and said one or more highly doped regions of a first conductivity type act as a source of said transistor.

12. The vertical transistor of claim 10 wherein said substrate acts as a source of said transistor and said one or more highly doped regions of a first conductivity type act as a drain of said transistor.

13. The vertical transistor of claim 8 further comprising:

one or more buried regions of a second conductivity type within said epitaxial layer, said one or more buried regions being in rectifying contact with said gates and sufficiently proximate to said one or more channels so as to sink minority carriers within said one or more channels.

14. The vertical transistor of claim 9 further comprising one or more buried regions of a first conductivity type, each within a corresponding buried region of a second conductivity type within said epitaxial layer, said one or more buried regions of a first conductivity type being in electrical contat with each other and with said gates and said one or more buried regions of a second conductivity type being sufficiently proximate to said one or more channels so as to sink minority carriers within said one or more channels.

15. The vertical transistor of claim 14 wherein each of said one or more buried regions of a first conductivity type is associated with one of said one or more channels.

16. The vertical transistor of claim 14 wherein each of said one or more buried regions of a first conductivity type is associated with one of said gates and each is approximately bisected by said associated gate.