Structure for contacting devices in three dimensional circuitry

• US 4,791,463 A
• Filed: 11/22/1985
• Issued: 12/13/1988
• Est. Priority Date: 10/31/1984
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Malhi, Satwinder S.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Crane, Sara W.
• Application Number:
  US06/801,037
• Time in Patent Office: 1,117 Days
• Field of Search: 357/23.6, 357/23.4, 357/23.1, 357/41, 357/51, 357/55, 357/23.12
• US Class Current: 257/302
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

The present invention is described in conjunction with the fabrication of a dRAM cell which an important application of the present invention. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell transistor is formed on the sidewalls of a substrate trench containing the cell capacitor; the word and bit lines cross over this trench. This stacking of the transistor on top of the capacitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells. One capacitor plate and the transistor channel and source region are formed in the bulk sidewall of the trench and the transistor gate and the other plate of the capacitor are both formed in polysilicon in the trench but separated from each other by an oxide layer inside the trench. The signal charge is stored on the polysilicon capacitor plate by an electrical connection of the source region with the polysilicon capacitor plate. The described embodiment provides an electrical connection which allows separate connection to the capacitor.

Claims

1. An integrated circuit component comprising:

a substrate including at least one tenth therein, wherein each trench surrounds a portion of the substrate;

each trench being surrounded by substrate trench sides and a substrate trench bottom;

a first insulating layer lining at least in part the trench sides and the trench bottom;

a first conductive material within each trench;

an outer source region, surrounding an associated trench, being situated substantially along the trench sides and contacting the first conductive material at a first location along the trench sides;

an inner source region being situated substantially along the trench sides on the portion of the substrate surrounded by the trench and being substantially concentric with a corresponding outer source region, the inner source region contacting the first conductive material at a second location along the trench sides;

an outer drain region, surrounding an associated trench and being situated substantially along the trench sides though separated from an associated outer source region so as to define a first channel region between the outer source region and the outer drain region;

an inner drain region being situated substantially along the trench sides on the portion of the substrate surrounded by the trench and being substantially concentric with a corresponding outer drain region though separated from the inner source region so as to define a second channel region between the inner source region and the inner drain region;

the drain and source regions being of a predetermined carrier type;

a second conductive material at least partially within each trench enclosing the first conductive material in an area bound by the second conductive material and the substrate sides and being separated from the channel regions by the first insulating layer so as to provide a gate region for the drain regions and the source regions;

a second insulating layer between the first conductive material and the second conductive material;

a well region, common to each trench, of the same carrier type as the drain and source regions, within the portion of the substrate surrounded by each trench and within a portion of the substrate around each trench, whereby the first conductive material forms a capacitor with the substrate and the first insulating layer and whereby the first conductive material can be accessed by a circuit connection which includes the drain regions, the well region, the channel regions and the source regions, thereby allowing access to all capacitor for testing purposes.

2. The integrated circuit component as recited in claim 1 which further comprises a third conductive material contacting the drain regions but out of direct contact with the substrate, the first and the second conductive materials.

3. The integrated circuit component as recited in claim 1 wherein the majority carrier concentration of the substrate substantially surrounding the first conductive material is of a higher carrier concentration than that in the substrate outside of the well in which the outer drain regions and outer source regions lie.

4. The integrated circuit component as recited in claim 1 wherein the source regions contact the first conductive material and the drain regions contact the third conductive material through polycrystalline silicon connections.

5. The integrated circuit component as recited in claim 1 which further comprises a field oxide layer between the third conductive material and the substrate.

6. An integrated circuit component comprising:

a substrate including at least one trench therein, wherein each trench surrounds a portion of the substrate;

each trench being surrounded by substrate trench sides and a substrate trench bottom;

a first insulating layer lining at least in part the trench sides and the trench bottom;

a first conductive material within each trench surrounding the portion of the substrate surrounded by each trench;

a polycrystalline silicon outer source connector associated with each trench;

an outer source region surrounding an associated trench, and being situated substantially along the trench sides and contacting the first conductive material through that trench'"'"'s associated polycrystalline silicon outer source connector at a first location along the trench sides;

a polycrystalline silicon inner source connector associated with each trench;

an inner source region being situated substantially along the trench sides on the portion of the substrate surrounded by the trench and being substantially concentric with a corresponding outer source region, the inner source region contacting the first conductive material through the trench'"'"'s associated polycrystalline silicon inner source connector at a second location along the trench sides;

an outer drain region, surrounding an associated trench, and being situated substantially along the trench sides though separated from an associated outer source region so as to define a first channel region between the outer source region and the outer drain region;

an inner drain region being situated substantially along the trench sides on the portion of the substrate surrounded by the trench and being substantially concentric with a corresponding outer drain region though separated from the inner source region so as to define a second channel region between the inner source region and the inner drain region;

the drain and source regions being of a predetermined carrier type;

a second conductive material at least partially within each trench enclosing the first conductive material in an area bound by itself and the substrate sides and being separated from the channel regions by the first insulating layer so as to provide a gate region for the drain regions and the source regions;

a second insulating layer between the first conductive material and the second conductive material;

a polycrystalline silicon drain connector associated with each drain;

a third conductive material contacting each drain region through its associated polycrystalline silicon drain connector, the third conductive material being out of direct contact with the substrate, the first and the second conductive materials; and

a field oxide layer between the third conductive material and the substrate;

a well region, common to each trench, of the same carrier type as the drain and source regions, within the portion of the substrate surrounded by each trench and within a portion of the substrate around each trench;

the majority carrier concentration of the substrate substantially surrounding the first conductive material being of a higher carrier concentration than that in the substrate outside of the well in which the outer drain regions and the outer source regions lie, whereby the first conductive material forms a capacitor with the substrate and the first insulating layer and whereby the first conductive material can be accessed by a circuit connection which includes the drain regions, the well region, the channel regions and the source regions, thereby allowing access to all capacitor for testing purposes.