Method of and apparatus for checking geometry of multi-layer patterns for IC structures

• US 4,791,586 A
• Filed: 12/23/1985
• Issued: 12/13/1988
• Est. Priority Date: 12/26/1984
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Ninomiya, Takanori, Maeda, Shunji, Kubota, Hitoshi, Makihira, Hiroshi, Nakagawa, Yasuo, Fushimi, Satoru
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): TRANS, VINCENT N
• Application Number:
  US06/812,928
• Time in Patent Office: 1,086 Days
• Field of Search: 364/491, 364/507, 364/552, 364/488, 364/489, 364/490, 364/571, 382/8, 382/21, 382/27, 382/34, 356/237, 356/394, 358/106, 358/101, 324/73 PC
• US Class Current: 716/112
• CPC Class Codes: G06T 2207/10056 Microscopic image
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/001 using an image reference approach

Abstract

Method of and apparatus for checking the geometry of multi-layer patterns for IC structures having identical functions, each of the multi-layer patterns including layer patterns arranged in different level layers, wherein electrical image signals corresponding to any two of the multi-layer patterns and having more than two levels are registered with each other and then compared to determine unmatched and matched portions. The comparison of the registered electric image signals may be performed with respect to their amplitude or their gradients. The registration and comparison of two electric image signals may be repeated for all of the layer patterns with the matched portions being no longer subjected to the registration and comparison. A defect detection signal is produced from finally unmatched portions, if any, of the electric image signals having undergone the said registration and comparison.

Claims

1. A method of checking the geometry of multi-layer patterns wherein images of corresponding portions on two of a plurality of identical circuit patterns on a specimen are detected to produce detection signals indicative of the corresponding portions in levels in terms of brightness of the detection signals, and the detection signals are compared with each other to judge an unmatched portion as a defect, said method comprising the steps of:

(a) registering the two detection signals;

(b) comparing levels of brightness of the two detection signals to judge that a portion of the detection signal at which the difference in brightness is less than a threshold level is normal and to define the normal portion as a "Don'"'"'t Care" portion;

(c) masking the detection signal at the "Don'"'"'t Care" portion to inhibit the use of the "Don'"'"'t Care" portion for the following registration and defect judgement;

(d) sequentially repeating said steps (a) to (c) for each layer of said multi-layer pattern to detect a region finally screened out of said "Don'"'"'t Care" portion as a defect.

2. An apparatus for checking the geometry of multilayer patterns wherein images of corresponding portions on two of a plurality of identical circuit patterns on a specimen are detected to produce detection signals indicative of the corresponding portions in levels in terms of brightness of the detection signals, and the detection signals are compared with each other to judge an unmatched portion as a defect, said apparatus comprising a plurality of defect detecting circuits connected in series by the same number as layers in said multi-layer pattern, each defect detecting circuit including:

means for registering the two detection signals;

means for comparing levels of brightness of the two detection signals to judge that a portion of the detection signal at which the difference in brightness is less than a threshold level is normal and to define the normal portion as a "Don'"'"'t Care" portion; and

means for masking the detection signal at the "Don'"'"'t Care" portion.

3. An apparatus for checking the geometry of patterns comprising:

two photoelectric converters receiving images of two patterns on an object to be checked and producing two detection signals used for comparing the images with each other;

registering means for correcting misregistration between the two detection signals on the basis of differences therebetween;

a difference image threshold circuit for converting differences between the two corrected detection signals into binary signals and producing the binary signals as defect candidates;

window region establishing circuit for applying a window on the defect candidates;

two gradient detecting circuits for detecting gradients of the corrected detection signals within the window; and

a comparing circuit for comparing the two gradients to produce an output signal when the difference between the two gradients exceeds a predetermined value.

4. An apparatus according to claim 3 wherein said photoelectric converter comprises a linear image sensor.

5. An apparatus according to claim 3 wherein said difference image threshold circuit comprises a subtracter for receiving said two corrected detection signal, an exclusive OR element for exclusive ORing an output signal of the subtracter and a sign signal, and a comparator for comparing an output signal of the exclusive OR circuit with a predetermined threshold level.

6. An apparatus according to claim 3 wherein said window region establishing circuit comprises shift registers for delaying an output signal of said difference image threshold circuit by one scanning time of said photoelectric converter, a serial/parallel conversion register for receiving the output signal of said different image threshold circuit directly or through said shift registers, and an AND element for receiving output signals of the serial/parallel conversion register.

7. An apparatus according to claim 3 wherein said window region establishing circuit has a window of a size between 2×

2 pixels and n×

n pixels (n;

natural number being not less than

     3) which are practically determined by the processing speed.

8. An apparatus according to claim 3 wherein said gradient detecting circuit has a window of a size between 3×

3 pixels and n×

n pixels (n;

natural number being more than

     3).

9. An apparatus according to claim 3 wherein said gradient detecting circuit comprises shift registers for delaying output signals of said registering means by one scanning time of said photoelectric converter, a serial/parallel conversion register for receiving the output signals of said registering means directly or through the shift registers, and subtracters, whereby said shift registers and serial/parallel conversion register cooperate to select pixels in synchronism with an output signal of said window region establishing circuit, said signals corresponding to two of the selected pixel are subtracted from each other by each subtracter to detect a gradient.

10. An apparatus for checking the geometry of patterns comprising:

two photoelectric converters receiving images of two patterns on an object to be checked and producing two detection signals used for comparing the images with each other;

registering means for correcting misregistration between the two detection signals on the basis of differences therebetween;

a difference image window region establishing and threshold circuit for recognizing differences between the two corrected detection signals as defect candidates to apply a window on the defect candidates and to convert the differences into binary signals;

two gradient detecting circuits for detecting gradients of the corrected detection signal within the window; and

a comparing circuit for comparing the two gradients to produce an output signal where the difference between the two gradients exceeds a predetermined value.

11. An apparatus according to claim 10 wherein said photoelectric converter comprises a linear image sensor.

12. An apparatus according to claim 10 wherein said difference image window region establishing and threshold circuit has a window of a size between 2×

2 pixels and n×

n pixels (n;

natural number being not less than

     3) which are practically determined by the processing speed.

13. An apparatus according to claim 10 wherein said difference image window region establishing and threshold circuit comprises a subtracter for receiving said two corrected detection signals, an exclusive OR element for exclusive ORing an output signal of the subtracter and a sign signal, a shift register for delaying an output signal of the exclusive OR element by one scanning time of said photoelectric converter, a serial/parallel conversion register for receiving the output signal of the exclusive OR element directly or through the shift register, an OR element for receiving output signals of the serial/parallel conversion register, and a comparator for comparing an output signal of the OR element with a predetermined threshold level.

14. An apparatus according to claim 10 wherein said gradient detecting circuit has a window of a size between 3×

3 pixels and n×

n pixels (n;

natural number being more than

     3).

15. An apparatus according to claim 10 wherein said gradient detecting circuit comprises shift registers for delaying output signals of said registering means by one scanning time of said photoelectric converter, serial/parallel conversion registers for receiving the output signals of said registering means directly or through the shift registers, and subtracters;

whereby said shift registers and serial/parallel conversion registers cooperate to select pixels in synchronism with an output signal of said difference image window region establishing and threshold circuit, and signals corresponding to two of the selected pixels are subtracted from each other by each subtracter to detect a gradient.

16. A method of checking the geometry of patterns comprising:

a first step of receiving images of two patterns on an object to be checked to produce two detection signals used for comparing the images with each other and correcting misregistration between the two detection signals;

a second step of comparing two corrected detection signals, converting differences between the two corrected detection signals into binary signals and applying a window on the binary signals; and

a third step of comparing the two corrected detection signals to detect gradients within the window and comparing the gradients to detect only a defect under no influence of the misregistration.

17. A method according to claim 16 wherein when linear image sensors receive the images, said first step comprises the step of effecting a two-dimensional scanning on the basis of self-scanning of the linear image sensors and movement of an X-Y stage carrying the object to be checked.

18. A method of checking the geometry of patterns comprising:

a first step of receiving images of two patterns on an object to be checked to produce two detection signals used for comparing the images with each other and correcting misregistration between the two detection signals;

a second step of comparing two corrected detection signals, applying a window on differences between the two corrected detection signals and converting the differences into binary signals; and

a third step of comparing the two corrected detection signals to detect gradients within the window and comparing the gradients to detect only a defect under no influence of the misregistration.

19. A method according to claim 18 wherein when linear image sensors receive the images, said first step comprises the step of effecting a two-dimensional scanning on the basis of self-scanning of the linear image sensors and movement of an X-Y stage carrying the object to be checked.

20. A method of checking the geometry of multi-layer patterns for IC structures having identical functions, each said multi-layer pattern for an IC structure including a plurality of layer patterns arranged in different level layers, the method comprising the steps of:

(a) registering a multi-layer pattern for a first any one of said IC structures with that for a second any one of said IC structures with respect to a first one of said plurality of layer patterns;

(b) comparing said registered multi-layer patterns to determine substantially matched and substantially unmatched portions with respect to said first one layer pattern;

(c) removing said matched portion out of those parts of patterns which are to be checked;

(d) repeating said steps (a) to (c) with respect to the remaining layer patterns of said multi-layer patterns for said first and second IC structures; and

(e) determining any finally substantially unmatched portion of said multi-layer pattern as a defect in a corresponding one of said multi-layer patterns under a checking operation.

21. A method of checking the geometry of multi-layer patterns for IC structures having identical functions, each said multi-layer pattern for an IC structure including a plurality of layer patterns arranged in different level layers, the method comprising the steps of:

(a) producing electric image signals from optical images of multi-layer patterns for any two of said IC structures, each of said electric image signals including image signal portions corresponding to said plurality of layer patterns for its associated IC structure;

(b) registering said electric image signals with each other with respect to one of said signal portions;

(c) comparing said registered electric image signals with each other to discriminate their substantially unmatched portions from substantially matched portions with respect to said one signal portion;

(d) masking said matched portions of said registered electric image signals so that any succeeding steps be performed at least on said unmatched portions of said electric image signals;

(e) repeating said steps (b) to (d) with respect to the remaining signal portions of said electric image signals; and

(f) producing a defect detection signal representative of any finally substantially unmatched portion of said electric image signals.

22. An apparatus for checking the geometry of multilayer patterns for IC structures having identical functions, said each multi-layer pattern for an IC structure including a plurality of layer patterns arranged in defferent level layers, the apparatus comprising:

first and second image sensing means for converting optical images of multi-layer patterns for any two of said IC structures to electric image signals, each of said electric image signals including signal portions corresponding to said plurality of layer patterns for its associated structure;

a plurality of unmatching detecting circuits connected in series, the most preceding one of said series-connected unmatching detecting circuits being connected with said first and second image sensing means to receive therefrom said electric image signals without substantial time delay;

masking circuits each interconnected between adjacent two of said series-connected unmatching detecting circuits; and

means connected with said first and second image sensing means for delaying said electric image signals, said delaying means being further connected with each of said masking circuits and each of said series-connected unmatching detecting circuits except the most preceding one to supply delayed signals produced from one of said electric image signals fed to said delaying means to said masking circuits so that each of said delayed signals is passed to that one of the associated unmatching detecting circuits which succeeds to the other one under control of the output of said other one unmatching detecting circuit and to supply delayed signals produced from the other one of said electric image signals to said unmatching detecting circuits, the delay time for said delayed signals to be supplied from said delaying means to one of said gate circuits and one of said unmatching detecting circuits being shorter for more preceding ones.

23. An apparatus according to claim 22, in which the number of said plurality of unmatching detecting circuits is not smaller than the number of said plurality of layer patterns arranged in different level layers.

24. An apparatus according to claim 22, in which:

each of said unmatching detecting circuits including registering means and matched portion removing means;

in the most preceding one of said unmatching detecting circuits, the registering means is connected with said first and second image sensing means to receive therefrom said electric image signals without substantial time delay and serving to register said electric image signals with each other with respect to one of said signal portions while said matched portion removing means includes a comparator for comparing the registered image signals fed from said registering means to produce a difference signal and a discriminator connected for reception of said difference signal from said comparator to produce a discrimination signal indicative of whether said difference signal exceeds a predetermined reference value or not, said discrimination signal being fed to the masking circuit connected with said most preceding unmatching detecting circuit;

in each of the other unmatching detecting circuits, the registering means is connected with its associated masking circuit and said delaying means to receive therefrom said delayed electric image signals and serving to register said delayed electric image signals with each other with respect to different one of said signal portions while said matched portion removing means includes a comparator for comparing the registered image signals fed from said registering means to produce a difference signal and a discriminator connected for reception of said difference signal from said comparator to produce a discrimination signal indicative of whether said difference signal exceeds a predetermined reference value or not.

25. An apparatus according to claim 24, in which each of said unmatching detecting circuits includes first and second edge detectors for processing said electric image signal portions of two layer patterns to generate edge detection signals indicative of edges of said layer patterns, a misregistration detecting circuit responsive to said edge detection signals for detecting misregistration between said two electric image signal portions and producing a shift signal indicative of an amount of shift of one of said electric image signal portions for said two layer patterns with respect to the other electric image signal, said shift amount causing said misregistration to be minimum, first and second delay circuits for delaying said electric image signal portions, and a registration circuit responsive to said shift signal for registering said electric image signal portions, said first and second edge detectors in said most receding one of said unmatching detecting circuits being in electrical connection with said first and second image sensing means, respectively, and said first and second edge detectors in each of said other unmatching detecting circuits being in electrical connection with said masking circuit and said delaying means, respectively.

26. A method of checking the geometry of patterns for IC structures having identical functions, comprising the steps of:

registering a pattern for a first any one of said IC structures with that for a second any one of said IC structures;

comparing the registered patterns for said first and second IC structures to detect differences therebetween;

comparing said differences with a predetermined threshold value;

determining gradients for each of said registered patterns;

establishing a window region for said registered patterns, said window region being narrower than the area of said patterns and being movable over said patterns;

detecting whether differences larger than said predetermined threshold value exist all over said window region;

comparing gradients for the pattern for said first IC structure with corresponding gradients for the pattern for said second IC structure when differences larger than said predetermined threshold value exist all over said window region; and

producing a defect dtection signal when said comparison of gradients results in a substantial difference.

27. An apparatus for checking the geometry of patterns for IC structures having identical functions, comprising:

first and second image sensing means for converting optical images of patterns for any two of said IC structures to electric image signals;

means for registering said electric image signals with each other;

first comprising means connected with said registering means for comparing said registered electric image signals to produce an error signal representative of differences between said registered electric image signals;

means connected with said first comparing means for determining whether the magnitudes of said error signal exceeds a predetermined threshold value or not;

means responsive to the output of said determining means for establishing a window region covering portions for said electric image signals which portions correspond to an area for said optical images;

means connected with said registering means for detecting gradients for said registered electric image signals under control of the output of said window region establishing means; and

second comparing means for comparing the detected gradients for said registered electric image signals to produce a defect detection signal when the comparison of the gradients results in a substantial difference.

28. A method of checking the geometry of multi-layer patterns for IC structures having identical functions, each said multi-layer pattern for an IC structure including a plurality of layer patterns arranged in different level layers, the method comprising the steps of:

(a) producing electric image signals from optical images of multi-layer patterns for any two of said IC structures, each of said electric image signals including image signal portions corresponding to said plurality of layer patterns for its associated IC structure;

(b) registering said electric image signals with each other with respect to one of said signal portions;

(c) comparing said registered electric image signals with each other to discriminate their substantially unmatched portions from substantially matched portions with respect to said one signal portion;

(d) masking said matched portions of said registered electric image signals so that any succeeding steps be performed at least one said unmatched portions of said electric image signals;

(e) repeating said steps (b) to (d) with respect to the remaining signal portions of said electric image signals;

(f) determining gradients for each of said registered electric image signals;

(g) comparing gradients for the registered electric image signal for one of said two IC structures with corresponding gradients for the registered electric image signal for the other one IC structure; and

(h) producing a defect detection signal when said comparison of gradients results in a substantial difference.

29. An apparatus for checking the geometry of multi-layer patterns for IC structures having identical functions, said each multi-layer pattern for an IC structure including a plurality of layer patterns arranged in different level layers, the apparatus comprising:

at least one image sensing means for converting optical images of multi-layer patterns for said IC structures to electric image signals, each of said electric image signals including signal portions corresponding to said plurality of layer patterns for its associated structure;

image memory means in an electrical connection with said image sensing means for storing therein image information contained in the output of said image sensing means, said image memory means being capable of being accessed to deliver electric image signals;

a plurality of unmatching detecting circuits connected in series each including means for registering electric image signals with each other, means for comparing said registered electric image signals fed from said registering means to produce a discrimination signal and means responsive to said discrimination signal for producing a defect detection signal, the registering means in the most preceding one of said series-connected unmatching detecting circuits being connected with said image sensing means and said image memory means to receive therefrom electric image signals to be checked, the registering means and comparing means in each of the other unmatching detecting circuits having a first masking circuit and a second masking circuit, respectively, the output of the registering means in one unmatching detecting circuit except in the most succeeding one being fed to the registering means in the immediately succeeding unmatching detecting circuit; and

a plurality of first delay means and a plurality of second delay means provided one first delay means and one second delay means for each adjacent two of said series-connected unmatching detecting circuits, said first and second delay means being arranged to receive the output of the comparing means in the preceding one of the adjacent two unmatching detecting circuits and to supply delayed outputs to the first and second masking circuits, respectively, in the succeeding one of the adjacent two unmatching detecting circuits so that registration and comparison by the registering and comparing means in the succeeding unmatching detecting circuit with respect to those portions of said registered electric image signals which have already been registered and discriminated as matched in the preceding unmatching detecting circuit are not repeated.

30. An apparatus according to claim 29, in which said defect detection signal producing means in each of said unmatching detecting circuits includes a detector responsive to the output of said comparing means for detecting gradients of each of said registered electric image signals fed from said registering means and a comparator for comparing the detected gradients to produce said defect detection signal when the comparison results in a substantial difference.